Options Controlling the Kind of Output
Compilation can involve up to four stages: preprocessing, compilation proper, assembly and linking, always in that order. GCC is capable of preprocessing and compiling several files either into several assembler input files, or into one assembler input file; then each assembler input file produces an object file, and linking combines all the object files (those newly compiled, and those specified as input) into an executable file.
For any given input file, the file name suffix determines what kind of compilation is done:
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file.c
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C source code that must be preprocessed.
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file.i
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C source code that should not be preprocessed.
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file.ii
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C++ source code that should not be preprocessed.
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file.m
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Objective-C source code. Note that you must link with the libobjc library to make an Objective-C program work.
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file.mi
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Objective-C source code that should not be preprocessed.
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file.mm
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file.M
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Objective-C++ source code. Note that you must link with the libobjc library to make an Objective-C++ program work. Note that .M refers to a literal capital M.
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file.mii
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Objective-C++ source code that should not be preprocessed.
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file.h
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C, C++, Objective-C or Objective-C++ header file to be turned into a precompiled header (default), or C, C++ header file to be turned into an Ada spec (via the -fdump-ada-spec switch).
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file.cc
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file.cp
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file.cxx
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file.cpp
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file.CPP
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file.c++
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file.C
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C++ source code that must be preprocessed. Note that in .cxx, the last two letters must both be literally x. Likewise, .C refers to a literal capital C.
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file.mm
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-
file.M
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Objective-C++ source code that must be preprocessed.
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file.mii
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Objective-C++ source code that should not be preprocessed.
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file.hh
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file.H
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file.hp
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file.hxx
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file.hpp
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file.HPP
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file.h++
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file.tcc
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C++ header file to be turned into a precompiled header or Ada spec.
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file.f
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file.for
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file.ftn
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Fixed form Fortran source code that should not be preprocessed.
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file.F
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file.FOR
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file.fpp
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file.FPP
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file.FTN
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Fixed form Fortran source code that must be preprocessed (with the traditional preprocessor).
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file.f90
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file.f95
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file.f03
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file.f08
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Free form Fortran source code that should not be preprocessed.
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file.F90
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file.F95
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file.F03
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file.F08
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Free form Fortran source code that must be preprocessed (with the traditional preprocessor).
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file.go
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Go source code.
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file.ads
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Ada source code file that contains a library unit declaration (a declaration of a package, subprogram, or generic, or a generic instantiation), or a library unit renaming declaration (a package, generic, or subprogram renaming declaration). Such files are also called specs.
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file.adb
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Ada source code file containing a library unit body (a subprogram or package body). Such files are also called bodies.
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file.s
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Assembler code.
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file.S
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file.sx
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Assembler code that must be preprocessed.
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other
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An object file to be fed straight into linking. Any file name with no recognized suffix is treated this way.
You can specify the input language explicitly with the -x option:
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-x language
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Specify explicitly the language for the following input files (rather than letting the compiler choose a default based on the file name suffix). This option applies to all following input files until the next -x option. Possible values for language are:
c c-header cpp-output
c++ c++-header c++-cpp-output
objective-c objective-c-header objective-c-cpp-output
objective-c++ objective-c++-header objective-c++-cpp-output
assembler assembler-with-cpp
ada
f77 f77-cpp-input f95 f95-cpp-input
go
java
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-x none
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Turn off any specification of a language, so that subsequent files are handled according to their file name suffixes (as they are if -x has not been used at all).
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-pass-exit-codes
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Normally the gcc program exits with the code of 1 if any phase of the compiler returns a non-success return code. If you specify -pass-exit-codes, the gcc program instead returns with the numerically highest error produced by any phase returning an error indication. The C, C++, and Fortran front ends return 4 if an internal compiler error is encountered.
If you only want some of the stages of compilation, you can use -x (or filename suffixes) to tell gcc where to start, and one of the options -c, -S, or -E to say where gcc is to stop. Note that some combinations (for example, -x cpp-output -E) instruct gcc to do nothing at all.
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-c
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Compile or assemble the source files, but do not link. The linking stage simply is not done. The ultimate output is in the form of an object file for each source file.
By default, the object file name for a source file is made by replacing the suffix .c, .i, .s, etc., with .o.
Unrecognized input files, not requiring compilation or assembly, are ignored.
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-S
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Stop after the stage of compilation proper; do not assemble. The output is in the form of an assembler code file for each non-assembler input file specified.
By default, the assembler file name for a source file is made by replacing the suffix .c, .i, etc., with .s.
Input files that don't require compilation are ignored.
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-E
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Stop after the preprocessing stage; do not run the compiler proper. The output is in the form of preprocessed source code, which is sent to the standard output.
Input files that don't require preprocessing are ignored.
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-o file
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Place output in file file. This applies to whatever sort of output is being produced, whether it be an executable file, an object file, an assembler file or preprocessed C code.
If -o is not specified, the default is to put an executable file in a.out, the object file for source.suffix in source.o, its assembler file in source.s, a precompiled header file in source.suffix.gch, and all preprocessed C source on standard output.
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-v
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Print (on standard error output) the commands executed to run the stages of compilation. Also print the version number of the compiler driver program and of the preprocessor and the compiler proper.
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-###
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Like -v except the commands are not executed and arguments are quoted unless they contain only alphanumeric characters or "./-_". This is useful for shell scripts to capture the driver-generated command lines.
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-pipe
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Use pipes rather than temporary files for communication between the various stages of compilation. This fails to work on some systems where the assembler is unable to read from a pipe; but the GNU assembler has no trouble.
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--help
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Print (on the standard output) a description of the command-line options understood by gcc. If the -v option is also specified then --help is also passed on to the various processes invoked by gcc, so that they can display the command-line options they accept. If the -Wextra option has also been specified (prior to the --help option), then command-line options that have no documentation associated with them are also displayed.
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--target-help
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Print (on the standard output) a description of target-specific command-line options for each tool. For some targets extra target-specific information may also be printed.
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--help={class|[^]qualifier}[,...]
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Print (on the standard output) a description of the command-line options understood by the compiler that fit into all specified classes and qualifiers. These are the supported classes:
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optimizers
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Display all of the optimization options supported by the compiler.
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warnings
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Display all of the options controlling warning messages produced by the compiler.
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target
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Display target-specific options. Unlike the --target-help option however, target-specific options of the linker and assembler are not displayed. This is because those tools do not currently support the extended --help= syntax.
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params
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Display the values recognized by the --param option.
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language
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Display the options supported for language, where language is the name of one of the languages supported in this version of GCC.
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common
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Display the options that are common to all languages.
These are the supported qualifiers:
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undocumented
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Display only those options that are undocumented.
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joined
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Display options taking an argument that appears after an equal sign in the same continuous piece of text, such as: --help=target.
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separate
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Display options taking an argument that appears as a separate word following the original option, such as: -o output-file.
Thus for example to display all the undocumented target-specific switches supported by the compiler, use:
--help=target,undocumented
The sense of a qualifier can be inverted by prefixing it with the
^ character, so for example to display all binary warning options (i.e., ones that are either on or off and that do not take an argument) that have a description, use:
--help=warnings,^joined,^undocumented
The argument to
--help= should not consist solely of inverted qualifiers.
Combining several classes is possible, although this usually restricts the output so much that there is nothing to display. One case where it does work, however, is when one of the classes is
target. For example, to display all the target-specific optimization options, use:
--help=target,optimizers
The
--help= option can be repeated on the command line. Each successive use displays its requested class of options, skipping those that have already been displayed.
If the
-Q option appears on the command line before the
--help= option, then the descriptive text displayed by
--help= is changed. Instead of describing the displayed options, an indication is given as to whether the option is enabled, disabled or set to a specific value (assuming that the compiler knows this at the point where the
--help= option is used).
Here is a truncated example from the ARM port of
gcc:
% gcc -Q -mabi=2 --help=target -c
The following options are target specific:
-mabi= 2
-mabort-on-noreturn [disabled]
-mapcs [disabled]
The output is sensitive to the effects of previous command-line options, so for example it is possible to find out which optimizations are enabled at
-O2 by using:
-Q -O2 --help=optimizers
Alternatively you can discover which binary optimizations are enabled by
-O3 by using:
gcc -c -Q -O3 --help=optimizers > /tmp/O3-opts
gcc -c -Q -O2 --help=optimizers > /tmp/O2-opts
diff /tmp/O2-opts /tmp/O3-opts | grep enabled
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-no-canonical-prefixes
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Do not expand any symbolic links, resolve references to /../ or /./, or make the path absolute when generating a relative prefix.
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--version
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Display the version number and copyrights of the invoked GCC.
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-wrapper
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Invoke all subcommands under a wrapper program. The name of the wrapper program and its parameters are passed as a comma separated list.
gcc -c t.c -wrapper gdb,--args
This invokes all subprograms of gcc under gdb --args, thus the invocation of cc1 is gdb --args cc1 ....
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-fplugin=name.so
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Load the plugin code in file name.so, assumed to be a shared object to be dlopen'd by the compiler. The base name of the shared object file is used to identify the plugin for the purposes of argument parsing (See -fplugin-arg-name-key=value below). Each plugin should define the callback functions specified in the Plugins API.
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-fplugin-arg-name-key=value
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Define an argument called key with a value of value for the plugin called name.
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-fdump-ada-spec[-slim]
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For C and C++ source and include files, generate corresponding Ada specs.
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-fada-spec-parent=unit
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In conjunction with -fdump-ada-spec[-slim] above, generate Ada specs as child units of parent unit.
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-fdump-go-spec=file
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For input files in any language, generate corresponding Go declarations in file. This generates Go "const", "type", "var", and "func" declarations which may be a useful way to start writing a Go interface to code written in some other language.
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@file
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Read command-line options from file. The options read are inserted in place of the original @ file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed.
Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @ file options; any such options will be processed recursively.
Options That Control Optimization
These options control various sorts of optimizations.
Without any optimization option, the compiler's goal is to reduce the cost of compilation and to make debugging produce the expected results. Statements are independent: if you stop the program with a breakpoint between statements, you can then assign a new value to any variable or change the program counter to any other statement in the function and get exactly the results you expect from the source code.
Turning on optimization flags makes the compiler attempt to improve the performance and/or code size at the expense of compilation time and possibly the ability to debug the program.
The compiler performs optimization based on the knowledge it has of the program. Compiling multiple files at once to a single output file mode allows the compiler to use information gained from all of the files when compiling each of them.
Not all optimizations are controlled directly by a flag. Only optimizations that have a flag are listed in this section.
Most optimizations are only enabled if an -O level is set on the command line. Otherwise they are disabled, even if individual optimization flags are specified.
Depending on the target and how GCC was configured, a slightly different set of optimizations may be enabled at each -O level than those listed here. You can invoke GCC with -Q --help=optimizers to find out the exact set of optimizations that are enabled at each level.
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-O
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-O1
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Optimize. Optimizing compilation takes somewhat more time, and a lot more memory for a large function.
With -O, the compiler tries to reduce code size and execution time, without performing any optimizations that take a great deal of compilation time.
-O turns on the following optimization flags:
-fauto-inc-dec -fcompare-elim -fcprop-registers -fdce -fdefer-pop -fdelayed-branch -fdse -fguess-branch-probability -fif-conversion2 -fif-conversion -fipa-pure-const -fipa-profile -fipa-reference -fmerge-constants -fsplit-wide-types -ftree-bit-ccp -ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copyrename -ftree-dce -ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre -ftree-phiprop -ftree-slsr -ftree-sra -ftree-pta -ftree-ter -funit-at-a-time
-O also turns on -fomit-frame-pointer on machines where doing so does not interfere with debugging.
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-O2
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Optimize even more. GCC performs nearly all supported optimizations that do not involve a space-speed tradeoff. As compared to -O, this option increases both compilation time and the performance of the generated code.
-O2 turns on all optimization flags specified by -O. It also turns on the following optimization flags: -fthread-jumps -falign-functions -falign-jumps -falign-loops -falign-labels -fcaller-saves -fcrossjumping -fcse-follow-jumps -fcse-skip-blocks -fdelete-null-pointer-checks -fdevirtualize -fexpensive-optimizations -fgcse -fgcse-lm -fhoist-adjacent-loads -finline-small-functions -findirect-inlining -fipa-sra -foptimize-sibling-calls -fpartial-inlining -fpeephole2 -fregmove -freorder-blocks -freorder-functions -frerun-cse-after-loop -fsched-interblock -fsched-spec -fschedule-insns -fschedule-insns2 -fstrict-aliasing -fstrict-overflow -ftree-switch-conversion -ftree-tail-merge -ftree-pre -ftree-vrp
Please note the warning under -fgcse about invoking -O2 on programs that use computed gotos.
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-O3
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Optimize yet more. -O3 turns on all optimizations specified by -O2 and also turns on the -finline-functions, -funswitch-loops, -fpredictive-commoning, -fgcse-after-reload, -ftree-vectorize, -fvect-cost-model, -ftree-partial-pre and -fipa-cp-clone options.
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-O0
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Reduce compilation time and make debugging produce the expected results. This is the default.
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-Os
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Optimize for size. -Os enables all -O2 optimizations that do not typically increase code size. It also performs further optimizations designed to reduce code size.
-Os disables the following optimization flags: -falign-functions -falign-jumps -falign-loops -falign-labels -freorder-blocks -freorder-blocks-and-partition -fprefetch-loop-arrays -ftree-vect-loop-version
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-Ofast
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Disregard strict standards compliance. -Ofast enables all -O3 optimizations. It also enables optimizations that are not valid for all standard-compliant programs. It turns on -ffast-math and the Fortran-specific -fno-protect-parens and -fstack-arrays.
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-Og
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Optimize debugging experience. -Og enables optimizations that do not interfere with debugging. It should be the optimization level of choice for the standard edit-compile-debug cycle, offering a reasonable level of optimization while maintaining fast compilation and a good debugging experience.
If you use multiple -O options, with or without level numbers, the last such option is the one that is effective.
Options of the form -fflag specify machine-independent flags. Most flags have both positive and negative forms; the negative form of -ffoo is -fno-foo. In the table below, only one of the forms is listed---the one you typically use. You can figure out the other form by either removing no- or adding it.
The following options control specific optimizations. They are either activated by -O options or are related to ones that are. You can use the following flags in the rare cases when "fine-tuning" of optimizations to be performed is desired.
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-fno-default-inline
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Do not make member functions inline by default merely because they are defined inside the class scope (C++ only). Otherwise, when you specify -O, member functions defined inside class scope are compiled inline by default; i.e., you don't need to add inline in front of the member function name.
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-fno-defer-pop
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Always pop the arguments to each function call as soon as that function returns. For machines that must pop arguments after a function call, the compiler normally lets arguments accumulate on the stack for several function calls and pops them all at once.
Disabled at levels -O, -O2, -O3, -Os.
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-fforward-propagate
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Perform a forward propagation pass on RTL. The pass tries to combine two instructions and checks if the result can be simplified. If loop unrolling is active, two passes are performed and the second is scheduled after loop unrolling.
This option is enabled by default at optimization levels -O, -O2, -O3, -Os.
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-ffp-contract=style
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-ffp-contract=off disables floating-point expression contraction. -ffp-contract=fast enables floating-point expression contraction such as forming of fused multiply-add operations if the target has native support for them. -ffp-contract=on enables floating-point expression contraction if allowed by the language standard. This is currently not implemented and treated equal to -ffp-contract=off.
The default is -ffp-contract=fast.
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-fomit-frame-pointer
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Don't keep the frame pointer in a register for functions that don't need one. This avoids the instructions to save, set up and restore frame pointers; it also makes an extra register available in many functions. It also makes debugging impossible on some machines.
On some machines, such as the VAX, this flag has no effect, because the standard calling sequence automatically handles the frame pointer and nothing is saved by pretending it doesn't exist. The machine-description macro "FRAME_POINTER_REQUIRED" controls whether a target machine supports this flag.
Starting with GCC version 4.6, the default setting (when not optimizing for size) for 32-bit GNU/Linux x86 and 32-bit Darwin x86 targets has been changed to -fomit-frame-pointer. The default can be reverted to -fno-omit-frame-pointer by configuring GCC with the --enable-frame-pointer configure option.
Enabled at levels -O, -O2, -O3, -Os.
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-foptimize-sibling-calls
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Optimize sibling and tail recursive calls.
Enabled at levels -O2, -O3, -Os.
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-fno-inline
-
Do not expand any functions inline apart from those marked with the "always_inline" attribute. This is the default when not optimizing.
Single functions can be exempted from inlining by marking them with the "noinline" attribute.
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-finline-small-functions
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Integrate functions into their callers when their body is smaller than expected function call code (so overall size of program gets smaller). The compiler heuristically decides which functions are simple enough to be worth integrating in this way. This inlining applies to all functions, even those not declared inline.
Enabled at level -O2.
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-findirect-inlining
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Inline also indirect calls that are discovered to be known at compile time thanks to previous inlining. This option has any effect only when inlining itself is turned on by the -finline-functions or -finline-small-functions options.
Enabled at level -O2.
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-finline-functions
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Consider all functions for inlining, even if they are not declared inline. The compiler heuristically decides which functions are worth integrating in this way.
If all calls to a given function are integrated, and the function is declared "static", then the function is normally not output as assembler code in its own right.
Enabled at level -O3.
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-finline-functions-called-once
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Consider all "static" functions called once for inlining into their caller even if they are not marked "inline". If a call to a given function is integrated, then the function is not output as assembler code in its own right.
Enabled at levels -O1, -O2, -O3 and -Os.
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-fearly-inlining
-
Inline functions marked by "always_inline" and functions whose body seems smaller than the function call overhead early before doing -fprofile-generate instrumentation and real inlining pass. Doing so makes profiling significantly cheaper and usually inlining faster on programs having large chains of nested wrapper functions.
Enabled by default.
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-fipa-sra
-
Perform interprocedural scalar replacement of aggregates, removal of unused parameters and replacement of parameters passed by reference by parameters passed by value.
Enabled at levels -O2, -O3 and -Os.
-
-finline-limit=n
-
By default, GCC limits the size of functions that can be inlined. This flag allows coarse control of this limit. n is the size of functions that can be inlined in number of pseudo instructions.
Inlining is actually controlled by a number of parameters, which may be specified individually by using --param name=value. The -finline-limit=n option sets some of these parameters as follows:
-
max-inline-insns-single
-
is set to n/2.
-
max-inline-insns-auto
-
is set to n/2.
See below for a documentation of the individual parameters controlling inlining and for the defaults of these parameters.
Note: there may be no value to
-finline-limit that results in default behavior.
Note: pseudo instruction represents, in this particular context, an abstract measurement of function's size. In no way does it represent a count of assembly instructions and as such its exact meaning might change from one release to an another.
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-fno-keep-inline-dllexport
-
This is a more fine-grained version of -fkeep-inline-functions, which applies only to functions that are declared using the "dllexport" attribute or declspec
-
-fkeep-inline-functions
-
In C, emit "static" functions that are declared "inline" into the object file, even if the function has been inlined into all of its callers. This switch does not affect functions using the "extern inline" extension in GNU C90. In C++, emit any and all inline functions into the object file.
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-fkeep-static-consts
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Emit variables declared "static const" when optimization isn't turned on, even if the variables aren't referenced.
GCC enables this option by default. If you want to force the compiler to check if a variable is referenced, regardless of whether or not optimization is turned on, use the -fno-keep-static-consts option.
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-fmerge-constants
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Attempt to merge identical constants (string constants and floating-point constants) across compilation units.
This option is the default for optimized compilation if the assembler and linker support it. Use -fno-merge-constants to inhibit this behavior.
Enabled at levels -O, -O2, -O3, -Os.
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-fmerge-all-constants
-
Attempt to merge identical constants and identical variables.
This option implies -fmerge-constants. In addition to -fmerge-constants this considers e.g. even constant initialized arrays or initialized constant variables with integral or floating-point types. Languages like C or C++ require each variable, including multiple instances of the same variable in recursive calls, to have distinct locations, so using this option results in non-conforming behavior.
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-fmodulo-sched
-
Perform swing modulo scheduling immediately before the first scheduling pass. This pass looks at innermost loops and reorders their instructions by overlapping different iterations.
-
-fmodulo-sched-allow-regmoves
-
Perform more aggressive SMS-based modulo scheduling with register moves allowed. By setting this flag certain anti-dependences edges are deleted, which triggers the generation of reg-moves based on the life-range analysis. This option is effective only with -fmodulo-sched enabled.
-
-fno-branch-count-reg
-
Do not use "decrement and branch" instructions on a count register, but instead generate a sequence of instructions that decrement a register, compare it against zero, then branch based upon the result. This option is only meaningful on architectures that support such instructions, which include x86, PowerPC, IA-64 and S/390.
The default is -fbranch-count-reg.
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-fno-function-cse
-
Do not put function addresses in registers; make each instruction that calls a constant function contain the function's address explicitly.
This option results in less efficient code, but some strange hacks that alter the assembler output may be confused by the optimizations performed when this option is not used.
The default is -ffunction-cse
-
-fno-zero-initialized-in-bss
-
If the target supports a BSS section, GCC by default puts variables that are initialized to zero into BSS. This can save space in the resulting code.
This option turns off this behavior because some programs explicitly rely on variables going to the data section---e.g., so that the resulting executable can find the beginning of that section and/or make assumptions based on that.
The default is -fzero-initialized-in-bss.
-
-fmudflap -fmudflapth -fmudflapir
-
For front-ends that support it (C and C++), instrument all risky pointer/array dereferencing operations, some standard library string/heap functions, and some other associated constructs with range/validity tests. Modules so instrumented should be immune to buffer overflows, invalid heap use, and some other classes of C/C++ programming errors. The instrumentation relies on a separate runtime library ( libmudflap), which is linked into a program if -fmudflap is given at link time. Run-time behavior of the instrumented program is controlled by the MUDFLAP_OPTIONS environment variable. See "env MUDFLAP_OPTIONS=-help a.out" for its options.
Use -fmudflapth instead of -fmudflap to compile and to link if your program is multi-threaded. Use -fmudflapir, in addition to -fmudflap or -fmudflapth, if instrumentation should ignore pointer reads. This produces less instrumentation (and therefore faster execution) and still provides some protection against outright memory corrupting writes, but allows erroneously read data to propagate within a program.
-
-fthread-jumps
-
Perform optimizations that check to see if a jump branches to a location where another comparison subsumed by the first is found. If so, the first branch is redirected to either the destination of the second branch or a point immediately following it, depending on whether the condition is known to be true or false.
Enabled at levels -O2, -O3, -Os.
-
-fsplit-wide-types
-
When using a type that occupies multiple registers, such as "long long" on a 32-bit system, split the registers apart and allocate them independently. This normally generates better code for those types, but may make debugging more difficult.
Enabled at levels -O, -O2, -O3, -Os.
-
-fcse-follow-jumps
-
In common subexpression elimination (CSE), scan through jump instructions when the target of the jump is not reached by any other path. For example, when CSE encounters an "if" statement with an "else" clause, CSE follows the jump when the condition tested is false.
Enabled at levels -O2, -O3, -Os.
-
-fcse-skip-blocks
-
This is similar to -fcse-follow-jumps, but causes CSE to follow jumps that conditionally skip over blocks. When CSE encounters a simple "if" statement with no else clause, -fcse-skip-blocks causes CSE to follow the jump around the body of the "if".
Enabled at levels -O2, -O3, -Os.
-
-frerun-cse-after-loop
-
Re-run common subexpression elimination after loop optimizations are performed.
Enabled at levels -O2, -O3, -Os.
-
-fgcse
-
Perform a global common subexpression elimination pass. This pass also performs global constant and copy propagation.
Note: When compiling a program using computed gotos, a GCC extension, you may get better run-time performance if you disable the global common subexpression elimination pass by adding -fno-gcse to the command line.
Enabled at levels -O2, -O3, -Os.
-
-fgcse-lm
-
When -fgcse-lm is enabled, global common subexpression elimination attempts to move loads that are only killed by stores into themselves. This allows a loop containing a load/store sequence to be changed to a load outside the loop, and a copy/store within the loop.
Enabled by default when -fgcse is enabled.
-
-fgcse-sm
-
When -fgcse-sm is enabled, a store motion pass is run after global common subexpression elimination. This pass attempts to move stores out of loops. When used in conjunction with -fgcse-lm, loops containing a load/store sequence can be changed to a load before the loop and a store after the loop.
Not enabled at any optimization level.
-
-fgcse-las
-
When -fgcse-las is enabled, the global common subexpression elimination pass eliminates redundant loads that come after stores to the same memory location (both partial and full redundancies).
Not enabled at any optimization level.
-
-fgcse-after-reload
-
When -fgcse-after-reload is enabled, a redundant load elimination pass is performed after reload. The purpose of this pass is to clean up redundant spilling.
-
-faggressive-loop-optimizations
-
This option tells the loop optimizer to use language constraints to derive bounds for the number of iterations of a loop. This assumes that loop code does not invoke undefined behavior by for example causing signed integer overflows or out-of-bound array accesses. The bounds for the number of iterations of a loop are used to guide loop unrolling and peeling and loop exit test optimizations. This option is enabled by default.
-
-funsafe-loop-optimizations
-
This option tells the loop optimizer to assume that loop indices do not overflow, and that loops with nontrivial exit condition are not infinite. This enables a wider range of loop optimizations even if the loop optimizer itself cannot prove that these assumptions are valid. If you use -Wunsafe-loop-optimizations, the compiler warns you if it finds this kind of loop.
-
-fcrossjumping
-
Perform cross-jumping transformation. This transformation unifies equivalent code and saves code size. The resulting code may or may not perform better than without cross-jumping.
Enabled at levels -O2, -O3, -Os.
-
-fauto-inc-dec
-
Combine increments or decrements of addresses with memory accesses. This pass is always skipped on architectures that do not have instructions to support this. Enabled by default at -O and higher on architectures that support this.
-
-fdce
-
Perform dead code elimination (DCE) on RTL. Enabled by default at -O and higher.
-
-fdse
-
Perform dead store elimination (DSE) on RTL. Enabled by default at -O and higher.
-
-fif-conversion
-
Attempt to transform conditional jumps into branch-less equivalents. This includes use of conditional moves, min, max, set flags and abs instructions, and some tricks doable by standard arithmetics. The use of conditional execution on chips where it is available is controlled by "if-conversion2".
Enabled at levels -O, -O2, -O3, -Os.
-
-fif-conversion2
-
Use conditional execution (where available) to transform conditional jumps into branch-less equivalents.
Enabled at levels -O, -O2, -O3, -Os.
-
-fdelete-null-pointer-checks
-
Assume that programs cannot safely dereference null pointers, and that no code or data element resides there. This enables simple constant folding optimizations at all optimization levels. In addition, other optimization passes in GCC use this flag to control global dataflow analyses that eliminate useless checks for null pointers; these assume that if a pointer is checked after it has already been dereferenced, it cannot be null.
Note however that in some environments this assumption is not true. Use -fno-delete-null-pointer-checks to disable this optimization for programs that depend on that behavior.
Some targets, especially embedded ones, disable this option at all levels. Otherwise it is enabled at all levels: -O0, -O1, -O2, -O3, -Os. Passes that use the information are enabled independently at different optimization levels.
-
-fdevirtualize
-
Attempt to convert calls to virtual functions to direct calls. This is done both within a procedure and interprocedurally as part of indirect inlining ("-findirect-inlining") and interprocedural constant propagation ( -fipa-cp). Enabled at levels -O2, -O3, -Os.
-
-fexpensive-optimizations
-
Perform a number of minor optimizations that are relatively expensive.
Enabled at levels -O2, -O3, -Os.
-
-free
-
Attempt to remove redundant extension instructions. This is especially helpful for the x86-64 architecture, which implicitly zero-extends in 64-bit registers after writing to their lower 32-bit half.
Enabled for x86 at levels -O2, -O3.
-
-foptimize-register-move
-
-
-fregmove
-
Attempt to reassign register numbers in move instructions and as operands of other simple instructions in order to maximize the amount of register tying. This is especially helpful on machines with two-operand instructions.
Note -fregmove and -foptimize-register-move are the same optimization.
Enabled at levels -O2, -O3, -Os.
-
-fira-algorithm=algorithm
-
Use the specified coloring algorithm for the integrated register allocator. The algorithm argument can be priority, which specifies Chow's priority coloring, or CB, which specifies Chaitin-Briggs coloring. Chaitin-Briggs coloring is not implemented for all architectures, but for those targets that do support it, it is the default because it generates better code.
-
-fira-region=region
-
Use specified regions for the integrated register allocator. The region argument should be one of the following:
-
all
-
Use all loops as register allocation regions. This can give the best results for machines with a small and/or irregular register set.
-
mixed
-
Use all loops except for loops with small register pressure as the regions. This value usually gives the best results in most cases and for most architectures, and is enabled by default when compiling with optimization for speed ( -O, -O2, ...).
-
one
-
Use all functions as a single region. This typically results in the smallest code size, and is enabled by default for -Os or -O0.
-
-fira-hoist-pressure
-
Use IRA to evaluate register pressure in the code hoisting pass for decisions to hoist expressions. This option usually results in smaller code, but it can slow the compiler down.
This option is enabled at level -Os for all targets.
-
-fira-loop-pressure
-
Use IRA to evaluate register pressure in loops for decisions to move loop invariants. This option usually results in generation of faster and smaller code on machines with large register files (>= 32 registers), but it can slow the compiler down.
This option is enabled at level -O3 for some targets.
-
-fno-ira-share-save-slots
-
Disable sharing of stack slots used for saving call-used hard registers living through a call. Each hard register gets a separate stack slot, and as a result function stack frames are larger.
-
-fno-ira-share-spill-slots
-
Disable sharing of stack slots allocated for pseudo-registers. Each pseudo-register that does not get a hard register gets a separate stack slot, and as a result function stack frames are larger.
-
-fira-verbose=n
-
Control the verbosity of the dump file for the integrated register allocator. The default value is 5. If the value n is greater or equal to 10, the dump output is sent to stderr using the same format as n minus 10.
-
-fdelayed-branch
-
If supported for the target machine, attempt to reorder instructions to exploit instruction slots available after delayed branch instructions.
Enabled at levels -O, -O2, -O3, -Os.
-
-fschedule-insns
-
If supported for the target machine, attempt to reorder instructions to eliminate execution stalls due to required data being unavailable. This helps machines that have slow floating point or memory load instructions by allowing other instructions to be issued until the result of the load or floating-point instruction is required.
Enabled at levels -O2, -O3.
-
-fschedule-insns2
-
Similar to -fschedule-insns, but requests an additional pass of instruction scheduling after register allocation has been done. This is especially useful on machines with a relatively small number of registers and where memory load instructions take more than one cycle.
Enabled at levels -O2, -O3, -Os.
-
-fno-sched-interblock
-
Don't schedule instructions across basic blocks. This is normally enabled by default when scheduling before register allocation, i.e. with -fschedule-insns or at -O2 or higher.
-
-fno-sched-spec
-
Don't allow speculative motion of non-load instructions. This is normally enabled by default when scheduling before register allocation, i.e. with -fschedule-insns or at -O2 or higher.
-
-fsched-pressure
-
Enable register pressure sensitive insn scheduling before register allocation. This only makes sense when scheduling before register allocation is enabled, i.e. with -fschedule-insns or at -O2 or higher. Usage of this option can improve the generated code and decrease its size by preventing register pressure increase above the number of available hard registers and subsequent spills in register allocation.
-
-fsched-spec-load
-
Allow speculative motion of some load instructions. This only makes sense when scheduling before register allocation, i.e. with -fschedule-insns or at -O2 or higher.
-
-fsched-spec-load-dangerous
-
Allow speculative motion of more load instructions. This only makes sense when scheduling before register allocation, i.e. with -fschedule-insns or at -O2 or higher.
-
-fsched-stalled-insns
-
-
-fsched-stalled-insns=n
-
Define how many insns (if any) can be moved prematurely from the queue of stalled insns into the ready list during the second scheduling pass. -fno-sched-stalled-insns means that no insns are moved prematurely, -fsched-stalled-insns=0 means there is no limit on how many queued insns can be moved prematurely. -fsched-stalled-insns without a value is equivalent to -fsched-stalled-insns=1.
-
-fsched-stalled-insns-dep
-
-
-fsched-stalled-insns-dep=n
-
Define how many insn groups (cycles) are examined for a dependency on a stalled insn that is a candidate for premature removal from the queue of stalled insns. This has an effect only during the second scheduling pass, and only if -fsched-stalled-insns is used. -fno-sched-stalled-insns-dep is equivalent to -fsched-stalled-insns-dep=0. -fsched-stalled-insns-dep without a value is equivalent to -fsched-stalled-insns-dep=1.
-
-fsched2-use-superblocks
-
When scheduling after register allocation, use superblock scheduling. This allows motion across basic block boundaries, resulting in faster schedules. This option is experimental, as not all machine descriptions used by GCC model the CPU closely enough to avoid unreliable results from the algorithm.
This only makes sense when scheduling after register allocation, i.e. with -fschedule-insns2 or at -O2 or higher.
-
-fsched-group-heuristic
-
Enable the group heuristic in the scheduler. This heuristic favors the instruction that belongs to a schedule group. This is enabled by default when scheduling is enabled, i.e. with -fschedule-insns or -fschedule-insns2 or at -O2 or higher.
-
-fsched-critical-path-heuristic
-
Enable the critical-path heuristic in the scheduler. This heuristic favors instructions on the critical path. This is enabled by default when scheduling is enabled, i.e. with -fschedule-insns or -fschedule-insns2 or at -O2 or higher.
-
-fsched-spec-insn-heuristic
-
Enable the speculative instruction heuristic in the scheduler. This heuristic favors speculative instructions with greater dependency weakness. This is enabled by default when scheduling is enabled, i.e. with -fschedule-insns or -fschedule-insns2 or at -O2 or higher.
-
-fsched-rank-heuristic
-
Enable the rank heuristic in the scheduler. This heuristic favors the instruction belonging to a basic block with greater size or frequency. This is enabled by default when scheduling is enabled, i.e. with -fschedule-insns or -fschedule-insns2 or at -O2 or higher.
-
-fsched-last-insn-heuristic
-
Enable the last-instruction heuristic in the scheduler. This heuristic favors the instruction that is less dependent on the last instruction scheduled. This is enabled by default when scheduling is enabled, i.e. with -fschedule-insns or -fschedule-insns2 or at -O2 or higher.
-
-fsched-dep-count-heuristic
-
Enable the dependent-count heuristic in the scheduler. This heuristic favors the instruction that has more instructions depending on it. This is enabled by default when scheduling is enabled, i.e. with -fschedule-insns or -fschedule-insns2 or at -O2 or higher.
-
-freschedule-modulo-scheduled-loops
-
Modulo scheduling is performed before traditional scheduling. If a loop is modulo scheduled, later scheduling passes may change its schedule. Use this option to control that behavior.
-
-fselective-scheduling
-
Schedule instructions using selective scheduling algorithm. Selective scheduling runs instead of the first scheduler pass.
-
-fselective-scheduling2
-
Schedule instructions using selective scheduling algorithm. Selective scheduling runs instead of the second scheduler pass.
-
-fsel-sched-pipelining
-
Enable software pipelining of innermost loops during selective scheduling. This option has no effect unless one of -fselective-scheduling or -fselective-scheduling2 is turned on.
-
-fsel-sched-pipelining-outer-loops
-
When pipelining loops during selective scheduling, also pipeline outer loops. This option has no effect unless -fsel-sched-pipelining is turned on.
-
-fshrink-wrap
-
Emit function prologues only before parts of the function that need it, rather than at the top of the function. This flag is enabled by default at -O and higher.
-
-fcaller-saves
-
Enable allocation of values to registers that are clobbered by function calls, by emitting extra instructions to save and restore the registers around such calls. Such allocation is done only when it seems to result in better code.
This option is always enabled by default on certain machines, usually those which have no call-preserved registers to use instead.
Enabled at levels -O2, -O3, -Os.
-
-fcombine-stack-adjustments
-
Tracks stack adjustments (pushes and pops) and stack memory references and then tries to find ways to combine them.
Enabled by default at -O1 and higher.
-
-fconserve-stack
-
Attempt to minimize stack usage. The compiler attempts to use less stack space, even if that makes the program slower. This option implies setting the large-stack-frame parameter to 100 and the large-stack-frame-growth parameter to 400.
-
-ftree-reassoc
-
Perform reassociation on trees. This flag is enabled by default at -O and higher.
-
-ftree-pre
-
Perform partial redundancy elimination (PRE) on trees. This flag is enabled by default at -O2 and -O3.
-
-ftree-partial-pre
-
Make partial redundancy elimination (PRE) more aggressive. This flag is enabled by default at -O3.
-
-ftree-forwprop
-
Perform forward propagation on trees. This flag is enabled by default at -O and higher.
-
-ftree-fre
-
Perform full redundancy elimination (FRE) on trees. The difference between FRE and PRE is that FRE only considers expressions that are computed on all paths leading to the redundant computation. This analysis is faster than PRE, though it exposes fewer redundancies. This flag is enabled by default at -O and higher.
-
-ftree-phiprop
-
Perform hoisting of loads from conditional pointers on trees. This pass is enabled by default at -O and higher.
-
-fhoist-adjacent-loads
-
Speculatively hoist loads from both branches of an if-then-else if the loads are from adjacent locations in the same structure and the target architecture has a conditional move instruction. This flag is enabled by default at -O2 and higher.
-
-ftree-copy-prop
-
Perform copy propagation on trees. This pass eliminates unnecessary copy operations. This flag is enabled by default at -O and higher.
-
-fipa-pure-const
-
Discover which functions are pure or constant. Enabled by default at -O and higher.
-
-fipa-reference
-
Discover which static variables do not escape the compilation unit. Enabled by default at -O and higher.
-
-fipa-pta
-
Perform interprocedural pointer analysis and interprocedural modification and reference analysis. This option can cause excessive memory and compile-time usage on large compilation units. It is not enabled by default at any optimization level.
-
-fipa-profile
-
Perform interprocedural profile propagation. The functions called only from cold functions are marked as cold. Also functions executed once (such as "cold", "noreturn", static constructors or destructors) are identified. Cold functions and loop less parts of functions executed once are then optimized for size. Enabled by default at -O and higher.
-
-fipa-cp
-
Perform interprocedural constant propagation. This optimization analyzes the program to determine when values passed to functions are constants and then optimizes accordingly. This optimization can substantially increase performance if the application has constants passed to functions. This flag is enabled by default at -O2, -Os and -O3.
-
-fipa-cp-clone
-
Perform function cloning to make interprocedural constant propagation stronger. When enabled, interprocedural constant propagation performs function cloning when externally visible function can be called with constant arguments. Because this optimization can create multiple copies of functions, it may significantly increase code size (see --param ipcp-unit-growth=value). This flag is enabled by default at -O3.
-
-ftree-sink
-
Perform forward store motion on trees. This flag is enabled by default at -O and higher.
-
-ftree-bit-ccp
-
Perform sparse conditional bit constant propagation on trees and propagate pointer alignment information. This pass only operates on local scalar variables and is enabled by default at -O and higher. It requires that -ftree-ccp is enabled.
-
-ftree-ccp
-
Perform sparse conditional constant propagation (CCP) on trees. This pass only operates on local scalar variables and is enabled by default at -O and higher.
-
-ftree-switch-conversion
-
Perform conversion of simple initializations in a switch to initializations from a scalar array. This flag is enabled by default at -O2 and higher.
-
-ftree-tail-merge
-
Look for identical code sequences. When found, replace one with a jump to the other. This optimization is known as tail merging or cross jumping. This flag is enabled by default at -O2 and higher. The compilation time in this pass can be limited using max-tail-merge-comparisons parameter and max-tail-merge-iterations parameter.
-
-ftree-dce
-
Perform dead code elimination (DCE) on trees. This flag is enabled by default at -O and higher.
-
-ftree-builtin-call-dce
-
Perform conditional dead code elimination (DCE) for calls to built-in functions that may set "errno" but are otherwise side-effect free. This flag is enabled by default at -O2 and higher if -Os is not also specified.
-
-ftree-dominator-opts
-
Perform a variety of simple scalar cleanups (constant/copy propagation, redundancy elimination, range propagation and expression simplification) based on a dominator tree traversal. This also performs jump threading (to reduce jumps to jumps). This flag is enabled by default at -O and higher.
-
-ftree-dse
-
Perform dead store elimination (DSE) on trees. A dead store is a store into a memory location that is later overwritten by another store without any intervening loads. In this case the earlier store can be deleted. This flag is enabled by default at -O and higher.
-
-ftree-ch
-
Perform loop header copying on trees. This is beneficial since it increases effectiveness of code motion optimizations. It also saves one jump. This flag is enabled by default at -O and higher. It is not enabled for -Os, since it usually increases code size.
-
-ftree-loop-optimize
-
Perform loop optimizations on trees. This flag is enabled by default at -O and higher.
-
-ftree-loop-linear
-
Perform loop interchange transformations on tree. Same as -floop-interchange. To use this code transformation, GCC has to be configured with --with-ppl and --with-cloog to enable the Graphite loop transformation infrastructure.
-
-floop-interchange
-
Perform loop interchange transformations on loops. Interchanging two nested loops switches the inner and outer loops. For example, given a loop like:
DO J = 1, M
DO I = 1, N
A(J, I) = A(J, I) * C
ENDDO
ENDDO
loop interchange transforms the loop as if it were written:
DO I = 1, N
DO J = 1, M
A(J, I) = A(J, I) * C
ENDDO
ENDDO
which can be beneficial when "N" is larger than the caches, because in Fortran, the elements of an array are stored in memory contiguously by column, and the original loop iterates over rows, potentially creating at each access a cache miss. This optimization applies to all the languages supported by GCC and is not limited to Fortran. To use this code transformation, GCC has to be configured with --with-ppl and --with-cloog to enable the Graphite loop transformation infrastructure.
-
-floop-strip-mine
-
Perform loop strip mining transformations on loops. Strip mining splits a loop into two nested loops. The outer loop has strides equal to the strip size and the inner loop has strides of the original loop within a strip. The strip length can be changed using the loop-block-tile-size parameter. For example, given a loop like:
DO I = 1, N
A(I) = A(I) + C
ENDDO
loop strip mining transforms the loop as if it were written:
DO II = 1, N, 51
DO I = II, min (II + 50, N)
A(I) = A(I) + C
ENDDO
ENDDO
This optimization applies to all the languages supported by GCC and is not limited to Fortran. To use this code transformation, GCC has to be configured with --with-ppl and --with-cloog to enable the Graphite loop transformation infrastructure.
-
-floop-block
-
Perform loop blocking transformations on loops. Blocking strip mines each loop in the loop nest such that the memory accesses of the element loops fit inside caches. The strip length can be changed using the loop-block-tile-size parameter. For example, given a loop like:
DO I = 1, N
DO J = 1, M
A(J, I) = B(I) + C(J)
ENDDO
ENDDO
loop blocking transforms the loop as if it were written:
DO II = 1, N, 51
DO JJ = 1, M, 51
DO I = II, min (II + 50, N)
DO J = JJ, min (JJ + 50, M)
A(J, I) = B(I) + C(J)
ENDDO
ENDDO
ENDDO
ENDDO
which can be beneficial when "M" is larger than the caches, because the innermost loop iterates over a smaller amount of data which can be kept in the caches. This optimization applies to all the languages supported by GCC and is not limited to Fortran. To use this code transformation, GCC has to be configured with --with-ppl and --with-cloog to enable the Graphite loop transformation infrastructure.
-
-fgraphite-identity
-
Enable the identity transformation for graphite. For every SCoP we generate the polyhedral representation and transform it back to gimple. Using -fgraphite-identity we can check the costs or benefits of the GIMPLE -> GRAPHITE -> GIMPLE transformation. Some minimal optimizations are also performed by the code generator CLooG, like index splitting and dead code elimination in loops.
-
-floop-nest-optimize
-
Enable the ISL based loop nest optimizer. This is a generic loop nest optimizer based on the Pluto optimization algorithms. It calculates a loop structure optimized for data-locality and parallelism. This option is experimental.
-
-floop-parallelize-all
-
Use the Graphite data dependence analysis to identify loops that can be parallelized. Parallelize all the loops that can be analyzed to not contain loop carried dependences without checking that it is profitable to parallelize the loops.
-
-fcheck-data-deps
-
Compare the results of several data dependence analyzers. This option is used for debugging the data dependence analyzers.
-
-ftree-loop-if-convert
-
Attempt to transform conditional jumps in the innermost loops to branch-less equivalents. The intent is to remove control-flow from the innermost loops in order to improve the ability of the vectorization pass to handle these loops. This is enabled by default if vectorization is enabled.
-
-ftree-loop-if-convert-stores
-
Attempt to also if-convert conditional jumps containing memory writes. This transformation can be unsafe for multi-threaded programs as it transforms conditional memory writes into unconditional memory writes. For example,
for (i = 0; i < N; i++)
if (cond)
A[i] = expr;
is transformed to
for (i = 0; i < N; i++)
A[i] = cond ? expr : A[i];
potentially producing data races.
-
-ftree-loop-distribution
-
Perform loop distribution. This flag can improve cache performance on big loop bodies and allow further loop optimizations, like parallelization or vectorization, to take place. For example, the loop
DO I = 1, N
A(I) = B(I) + C
D(I) = E(I) * F
ENDDO
is transformed to
DO I = 1, N
A(I) = B(I) + C
ENDDO
DO I = 1, N
D(I) = E(I) * F
ENDDO
-
-ftree-loop-distribute-patterns
-
Perform loop distribution of patterns that can be code generated with calls to a library. This flag is enabled by default at -O3.
This pass distributes the initialization loops and generates a call to memset zero. For example, the loop
DO I = 1, N
A(I) = 0
B(I) = A(I) + I
ENDDO
is transformed to
DO I = 1, N
A(I) = 0
ENDDO
DO I = 1, N
B(I) = A(I) + I
ENDDO
and the initialization loop is transformed into a call to memset zero.
-
-ftree-loop-im
-
Perform loop invariant motion on trees. This pass moves only invariants that are hard to handle at RTL level (function calls, operations that expand to nontrivial sequences of insns). With -funswitch-loops it also moves operands of conditions that are invariant out of the loop, so that we can use just trivial invariantness analysis in loop unswitching. The pass also includes store motion.
-
-ftree-loop-ivcanon
-
Create a canonical counter for number of iterations in loops for which determining number of iterations requires complicated analysis. Later optimizations then may determine the number easily. Useful especially in connection with unrolling.
-
-fivopts
-
Perform induction variable optimizations (strength reduction, induction variable merging and induction variable elimination) on trees.
-
-ftree-parallelize-loops=n
-
Parallelize loops, i.e., split their iteration space to run in n threads. This is only possible for loops whose iterations are independent and can be arbitrarily reordered. The optimization is only profitable on multiprocessor machines, for loops that are CPU-intensive, rather than constrained e.g. by memory bandwidth. This option implies -pthread, and thus is only supported on targets that have support for -pthread.
-
-ftree-pta
-
Perform function-local points-to analysis on trees. This flag is enabled by default at -O and higher.
-
-ftree-sra
-
Perform scalar replacement of aggregates. This pass replaces structure references with scalars to prevent committing structures to memory too early. This flag is enabled by default at -O and higher.
-
-ftree-copyrename
-
Perform copy renaming on trees. This pass attempts to rename compiler temporaries to other variables at copy locations, usually resulting in variable names which more closely resemble the original variables. This flag is enabled by default at -O and higher.
-
-ftree-coalesce-inlined-vars
-
Tell the copyrename pass (see -ftree-copyrename) to attempt to combine small user-defined variables too, but only if they were inlined from other functions. It is a more limited form of -ftree-coalesce-vars. This may harm debug information of such inlined variables, but it will keep variables of the inlined-into function apart from each other, such that they are more likely to contain the expected values in a debugging session. This was the default in GCC versions older than 4.7.
-
-ftree-coalesce-vars
-
Tell the copyrename pass (see -ftree-copyrename) to attempt to combine small user-defined variables too, instead of just compiler temporaries. This may severely limit the ability to debug an optimized program compiled with -fno-var-tracking-assignments. In the negated form, this flag prevents SSA coalescing of user variables, including inlined ones. This option is enabled by default.
-
-ftree-ter
-
Perform temporary expression replacement during the SSA->normal phase. Single use/single def temporaries are replaced at their use location with their defining expression. This results in non-GIMPLE code, but gives the expanders much more complex trees to work on resulting in better RTL generation. This is enabled by default at -O and higher.
-
-ftree-slsr
-
Perform straight-line strength reduction on trees. This recognizes related expressions involving multiplications and replaces them by less expensive calculations when possible. This is enabled by default at -O and higher.
-
-ftree-vectorize
-
Perform loop vectorization on trees. This flag is enabled by default at -O3.
-
-ftree-slp-vectorize
-
Perform basic block vectorization on trees. This flag is enabled by default at -O3 and when -ftree-vectorize is enabled.
-
-ftree-vect-loop-version
-
Perform loop versioning when doing loop vectorization on trees. When a loop appears to be vectorizable except that data alignment or data dependence cannot be determined at compile time, then vectorized and non-vectorized versions of the loop are generated along with run-time checks for alignment or dependence to control which version is executed. This option is enabled by default except at level -Os where it is disabled.
-
-fvect-cost-model
-
Enable cost model for vectorization. This option is enabled by default at -O3.
-
-ftree-vrp
-
Perform Value Range Propagation on trees. This is similar to the constant propagation pass, but instead of values, ranges of values are propagated. This allows the optimizers to remove unnecessary range checks like array bound checks and null pointer checks. This is enabled by default at -O2 and higher. Null pointer check elimination is only done if -fdelete-null-pointer-checks is enabled.
-
-ftracer
-
Perform tail duplication to enlarge superblock size. This transformation simplifies the control flow of the function allowing other optimizations to do a better job.
-
-funroll-loops
-
Unroll loops whose number of iterations can be determined at compile time or upon entry to the loop. -funroll-loops implies -frerun-cse-after-loop. This option makes code larger, and may or may not make it run faster.
-
-funroll-all-loops
-
Unroll all loops, even if their number of iterations is uncertain when the loop is entered. This usually makes programs run more slowly. -funroll-all-loops implies the same options as -funroll-loops,
-
-fsplit-ivs-in-unroller
-
Enables expression of values of induction variables in later iterations of the unrolled loop using the value in the first iteration. This breaks long dependency chains, thus improving efficiency of the scheduling passes.
A combination of -fweb and CSE is often sufficient to obtain the same effect. However, that is not reliable in cases where the loop body is more complicated than a single basic block. It also does not work at all on some architectures due to restrictions in the CSE pass.
This optimization is enabled by default.
-
-fvariable-expansion-in-unroller
-
With this option, the compiler creates multiple copies of some local variables when unrolling a loop, which can result in superior code.
-
-fpartial-inlining
-
Inline parts of functions. This option has any effect only when inlining itself is turned on by the -finline-functions or -finline-small-functions options.
Enabled at level -O2.
-
-fpredictive-commoning
-
Perform predictive commoning optimization, i.e., reusing computations (especially memory loads and stores) performed in previous iterations of loops.
This option is enabled at level -O3.
-
-fprefetch-loop-arrays
-
If supported by the target machine, generate instructions to prefetch memory to improve the performance of loops that access large arrays.
This option may generate better or worse code; results are highly dependent on the structure of loops within the source code.
Disabled at level -Os.
-
-fno-peephole
-
-
-fno-peephole2
-
Disable any machine-specific peephole optimizations. The difference between -fno-peephole and -fno-peephole2 is in how they are implemented in the compiler; some targets use one, some use the other, a few use both.
-fpeephole is enabled by default. -fpeephole2 enabled at levels -O2, -O3, -Os.
-
-fno-guess-branch-probability
-
Do not guess branch probabilities using heuristics.
GCC uses heuristics to guess branch probabilities if they are not provided by profiling feedback ( -fprofile-arcs). These heuristics are based on the control flow graph. If some branch probabilities are specified by __builtin_expect, then the heuristics are used to guess branch probabilities for the rest of the control flow graph, taking the __builtin_expect info into account. The interactions between the heuristics and __builtin_expect can be complex, and in some cases, it may be useful to disable the heuristics so that the effects of __builtin_expect are easier to understand.
The default is -fguess-branch-probability at levels -O, -O2, -O3, -Os.
-
-freorder-blocks
-
Reorder basic blocks in the compiled function in order to reduce number of taken branches and improve code locality.
Enabled at levels -O2, -O3.
-
-freorder-blocks-and-partition
-
In addition to reordering basic blocks in the compiled function, in order to reduce number of taken branches, partitions hot and cold basic blocks into separate sections of the assembly and .o files, to improve paging and cache locality performance.
This optimization is automatically turned off in the presence of exception handling, for linkonce sections, for functions with a user-defined section attribute and on any architecture that does not support named sections.
-
-freorder-functions
-
Reorder functions in the object file in order to improve code locality. This is implemented by using special subsections ".text.hot" for most frequently executed functions and ".text.unlikely" for unlikely executed functions. Reordering is done by the linker so object file format must support named sections and linker must place them in a reasonable way.
Also profile feedback must be available to make this option effective. See -fprofile-arcs for details.
Enabled at levels -O2, -O3, -Os.
-
-fstrict-aliasing
-
Allow the compiler to assume the strictest aliasing rules applicable to the language being compiled. For C (and C++), this activates optimizations based on the type of expressions. In particular, an object of one type is assumed never to reside at the same address as an object of a different type, unless the types are almost the same. For example, an "unsigned int" can alias an "int", but not a "void*" or a "double". A character type may alias any other type.
Pay special attention to code like this:
union a_union {
int i;
double d;
};
int f() {
union a_union t;
t.d = 3.0;
return t.i;
}
The practice of reading from a different union member than the one most recently written to (called "type-punning") is common. Even with -fstrict-aliasing, type-punning is allowed, provided the memory is accessed through the union type. So, the code above works as expected. However, this code might not:
int f() {
union a_union t;
int* ip;
t.d = 3.0;
ip = &t.i;
return *ip;
}
Similarly, access by taking the address, casting the resulting pointer and dereferencing the result has undefined behavior, even if the cast uses a union type, e.g.:
int f() {
double d = 3.0;
return ((union a_union *) &d)->i;
}
The -fstrict-aliasing option is enabled at levels -O2, -O3, -Os.
-
-fstrict-overflow
-
Allow the compiler to assume strict signed overflow rules, depending on the language being compiled. For C (and C++) this means that overflow when doing arithmetic with signed numbers is undefined, which means that the compiler may assume that it does not happen. This permits various optimizations. For example, the compiler assumes that an expression like "i + 10 > i" is always true for signed "i". This assumption is only valid if signed overflow is undefined, as the expression is false if "i + 10" overflows when using twos complement arithmetic. When this option is in effect any attempt to determine whether an operation on signed numbers overflows must be written carefully to not actually involve overflow.
This option also allows the compiler to assume strict pointer semantics: given a pointer to an object, if adding an offset to that pointer does not produce a pointer to the same object, the addition is undefined. This permits the compiler to conclude that "p + u > p" is always true for a pointer "p" and unsigned integer "u". This assumption is only valid because pointer wraparound is undefined, as the expression is false if "p + u" overflows using twos complement arithmetic.
See also the -fwrapv option. Using -fwrapv means that integer signed overflow is fully defined: it wraps. When -fwrapv is used, there is no difference between -fstrict-overflow and -fno-strict-overflow for integers. With -fwrapv certain types of overflow are permitted. For example, if the compiler gets an overflow when doing arithmetic on constants, the overflowed value can still be used with -fwrapv, but not otherwise.
The -fstrict-overflow option is enabled at levels -O2, -O3, -Os.
-
-falign-functions
-
-
-falign-functions=n
-
Align the start of functions to the next power-of-two greater than n, skipping up to n bytes. For instance, -falign-functions=32 aligns functions to the next 32-byte boundary, but -falign-functions=24 aligns to the next 32-byte boundary only if this can be done by skipping 23 bytes or less.
-fno-align-functions and -falign-functions=1 are equivalent and mean that functions are not aligned.
Some assemblers only support this flag when n is a power of two; in that case, it is rounded up.
If n is not specified or is zero, use a machine-dependent default.
Enabled at levels -O2, -O3.
-
-falign-labels
-
-
-falign-labels=n
-
Align all branch targets to a power-of-two boundary, skipping up to n bytes like -falign-functions. This option can easily make code slower, because it must insert dummy operations for when the branch target is reached in the usual flow of the code.
-fno-align-labels and -falign-labels=1 are equivalent and mean that labels are not aligned.
If -falign-loops or -falign-jumps are applicable and are greater than this value, then their values are used instead.
If n is not specified or is zero, use a machine-dependent default which is very likely to be 1, meaning no alignment.
Enabled at levels -O2, -O3.
-
-falign-loops
-
-
-falign-loops=n
-
Align loops to a power-of-two boundary, skipping up to n bytes like -falign-functions. If the loops are executed many times, this makes up for any execution of the dummy operations.
-fno-align-loops and -falign-loops=1 are equivalent and mean that loops are not aligned.
If n is not specified or is zero, use a machine-dependent default.
Enabled at levels -O2, -O3.
-
-falign-jumps
-
-
-falign-jumps=n
-
Align branch targets to a power-of-two boundary, for branch targets where the targets can only be reached by jumping, skipping up to n bytes like -falign-functions. In this case, no dummy operations need be executed.
-fno-align-jumps and -falign-jumps=1 are equivalent and mean that loops are not aligned.
If n is not specified or is zero, use a machine-dependent default.
Enabled at levels -O2, -O3.
-
-funit-at-a-time
-
This option is left for compatibility reasons. -funit-at-a-time has no effect, while -fno-unit-at-a-time implies -fno-toplevel-reorder and -fno-section-anchors.
Enabled by default.
-
-fno-toplevel-reorder
-
Do not reorder top-level functions, variables, and "asm" statements. Output them in the same order that they appear in the input file. When this option is used, unreferenced static variables are not removed. This option is intended to support existing code that relies on a particular ordering. For new code, it is better to use attributes.
Enabled at level -O0. When disabled explicitly, it also implies -fno-section-anchors, which is otherwise enabled at -O0 on some targets.
-
-fweb
-
Constructs webs as commonly used for register allocation purposes and assign each web individual pseudo register. This allows the register allocation pass to operate on pseudos directly, but also strengthens several other optimization passes, such as CSE, loop optimizer and trivial dead code remover. It can, however, make debugging impossible, since variables no longer stay in a "home register".
Enabled by default with -funroll-loops.
-
-fwhole-program
-
Assume that the current compilation unit represents the whole program being compiled. All public functions and variables with the exception of "main" and those merged by attribute "externally_visible" become static functions and in effect are optimized more aggressively by interprocedural optimizers.
This option should not be used in combination with "-flto". Instead relying on a linker plugin should provide safer and more precise information.
-
-flto[=n]
-
This option runs the standard link-time optimizer. When invoked with source code, it generates GIMPLE (one of GCC's internal representations) and writes it to special ELF sections in the object file. When the object files are linked together, all the function bodies are read from these ELF sections and instantiated as if they had been part of the same translation unit.
To use the link-time optimizer, -flto needs to be specified at compile time and during the final link. For example:
gcc -c -O2 -flto foo.c
gcc -c -O2 -flto bar.c
gcc -o myprog -flto -O2 foo.o bar.o
The first two invocations to GCC save a bytecode representation of GIMPLE into special ELF sections inside foo.o and bar.o. The final invocation reads the GIMPLE bytecode from foo.o and bar.o, merges the two files into a single internal image, and compiles the result as usual. Since both foo.o and bar.o are merged into a single image, this causes all the interprocedural analyses and optimizations in GCC to work across the two files as if they were a single one. This means, for example, that the inliner is able to inline functions in bar.o into functions in foo.o and vice-versa.
Another (simpler) way to enable link-time optimization is:
gcc -o myprog -flto -O2 foo.c bar.c
The above generates bytecode for foo.c and bar.c, merges them together into a single GIMPLE representation and optimizes them as usual to produce myprog.
The only important thing to keep in mind is that to enable link-time optimizations the -flto flag needs to be passed to both the compile and the link commands.
To make whole program optimization effective, it is necessary to make certain whole program assumptions. The compiler needs to know what functions and variables can be accessed by libraries and runtime outside of the link-time optimized unit. When supported by the linker, the linker plugin (see -fuse-linker-plugin) passes information to the compiler about used and externally visible symbols. When the linker plugin is not available, -fwhole-program should be used to allow the compiler to make these assumptions, which leads to more aggressive optimization decisions.
Note that when a file is compiled with -flto, the generated object file is larger than a regular object file because it contains GIMPLE bytecodes and the usual final code. This means that object files with LTO information can be linked as normal object files; if -flto is not passed to the linker, no interprocedural optimizations are applied.
Additionally, the optimization flags used to compile individual files are not necessarily related to those used at link time. For instance,
gcc -c -O0 -flto foo.c
gcc -c -O0 -flto bar.c
gcc -o myprog -flto -O3 foo.o bar.o
This produces individual object files with unoptimized assembler code, but the resulting binary myprog is optimized at -O3. If, instead, the final binary is generated without -flto, then myprog is not optimized.
When producing the final binary with -flto, GCC only applies link-time optimizations to those files that contain bytecode. Therefore, you can mix and match object files and libraries with GIMPLE bytecodes and final object code. GCC automatically selects which files to optimize in LTO mode and which files to link without further processing.
There are some code generation flags preserved by GCC when generating bytecodes, as they need to be used during the final link stage. Currently, the following options are saved into the GIMPLE bytecode files: -fPIC, -fcommon and all the -m target flags.
At link time, these options are read in and reapplied. Note that the current implementation makes no attempt to recognize conflicting values for these options. If different files have conflicting option values (e.g., one file is compiled with -fPIC and another isn't), the compiler simply uses the last value read from the bytecode files. It is recommended, then, that you compile all the files participating in the same link with the same options.
If LTO encounters objects with C linkage declared with incompatible types in separate translation units to be linked together (undefined behavior according to ISO C99 6.2.7), a non-fatal diagnostic may be issued. The behavior is still undefined at run time.
Another feature of LTO is that it is possible to apply interprocedural optimizations on files written in different languages. This requires support in the language front end. Currently, the C, C++ and Fortran front ends are capable of emitting GIMPLE bytecodes, so something like this should work:
gcc -c -flto foo.c
g++ -c -flto bar.cc
gfortran -c -flto baz.f90
g++ -o myprog -flto -O3 foo.o bar.o baz.o -lgfortran
Notice that the final link is done with g++ to get the C++ runtime libraries and -lgfortran is added to get the Fortran runtime libraries. In general, when mixing languages in LTO mode, you should use the same link command options as when mixing languages in a regular (non-LTO) compilation; all you need to add is -flto to all the compile and link commands.
If object files containing GIMPLE bytecode are stored in a library archive, say libfoo.a, it is possible to extract and use them in an LTO link if you are using a linker with plugin support. To enable this feature, use the flag -fuse-linker-plugin at link time:
gcc -o myprog -O2 -flto -fuse-linker-plugin a.o b.o -lfoo
With the linker plugin enabled, the linker extracts the needed GIMPLE files from libfoo.a and passes them on to the running GCC to make them part of the aggregated GIMPLE image to be optimized.
If you are not using a linker with plugin support and/or do not enable the linker plugin, then the objects inside libfoo.a are extracted and linked as usual, but they do not participate in the LTO optimization process.
Link-time optimizations do not require the presence of the whole program to operate. If the program does not require any symbols to be exported, it is possible to combine -flto and -fwhole-program to allow the interprocedural optimizers to use more aggressive assumptions which may lead to improved optimization opportunities. Use of -fwhole-program is not needed when linker plugin is active (see -fuse-linker-plugin).
The current implementation of LTO makes no attempt to generate bytecode that is portable between different types of hosts. The bytecode files are versioned and there is a strict version check, so bytecode files generated in one version of GCC will not work with an older/newer version of GCC.
Link-time optimization does not work well with generation of debugging information. Combining -flto with -g is currently experimental and expected to produce wrong results.
If you specify the optional n, the optimization and code generation done at link time is executed in parallel using n parallel jobs by utilizing an installed make program. The environment variable MAKE may be used to override the program used. The default value for n is 1.
You can also specify -flto=jobserver to use GNU make's job server mode to determine the number of parallel jobs. This is useful when the Makefile calling GCC is already executing in parallel. You must prepend a + to the command recipe in the parent Makefile for this to work. This option likely only works if MAKE is GNU make.
This option is disabled by default.
-
-flto-partition=alg
-
Specify the partitioning algorithm used by the link-time optimizer. The value is either "1to1" to specify a partitioning mirroring the original source files or "balanced" to specify partitioning into equally sized chunks (whenever possible) or "max" to create new partition for every symbol where possible. Specifying "none" as an algorithm disables partitioning and streaming completely. The default value is "balanced". While "1to1" can be used as an workaround for various code ordering issues, the "max" partitioning is intended for internal testing only.
-
-flto-compression-level=n
-
This option specifies the level of compression used for intermediate language written to LTO object files, and is only meaningful in conjunction with LTO mode ( -flto). Valid values are 0 (no compression) to 9 (maximum compression). Values outside this range are clamped to either 0 or 9. If the option is not given, a default balanced compression setting is used.
-
-flto-report
-
Prints a report with internal details on the workings of the link-time optimizer. The contents of this report vary from version to version. It is meant to be useful to GCC developers when processing object files in LTO mode (via -flto).
Disabled by default.
-
-fuse-linker-plugin
-
Enables the use of a linker plugin during link-time optimization. This option relies on plugin support in the linker, which is available in gold or in GNU ld 2.21 or newer.
This option enables the extraction of object files with GIMPLE bytecode out of library archives. This improves the quality of optimization by exposing more code to the link-time optimizer. This information specifies what symbols can be accessed externally (by non-LTO object or during dynamic linking). Resulting code quality improvements on binaries (and shared libraries that use hidden visibility) are similar to "-fwhole-program". See -flto for a description of the effect of this flag and how to use it.
This option is enabled by default when LTO support in GCC is enabled and GCC was configured for use with a linker supporting plugins (GNU ld 2.21 or newer or gold).
-
-ffat-lto-objects
-
Fat LTO objects are object files that contain both the intermediate language and the object code. This makes them usable for both LTO linking and normal linking. This option is effective only when compiling with -flto and is ignored at link time.
-fno-fat-lto-objects improves compilation time over plain LTO, but requires the complete toolchain to be aware of LTO. It requires a linker with linker plugin support for basic functionality. Additionally, nm, ar and ranlib need to support linker plugins to allow a full-featured build environment (capable of building static libraries etc). GCC provides the gcc-ar, gcc-nm, gcc-ranlib wrappers to pass the right options to these tools. With non fat LTO makefiles need to be modified to use them.
The default is -ffat-lto-objects but this default is intended to change in future releases when linker plugin enabled environments become more common.
-
-fcompare-elim
-
After register allocation and post-register allocation instruction splitting, identify arithmetic instructions that compute processor flags similar to a comparison operation based on that arithmetic. If possible, eliminate the explicit comparison operation.
This pass only applies to certain targets that cannot explicitly represent the comparison operation before register allocation is complete.
Enabled at levels -O, -O2, -O3, -Os.
-
-fuse-ld=bfd
-
Use the bfd linker instead of the default linker.
-
-fuse-ld=gold
-
Use the gold linker instead of the default linker.
-
-fcprop-registers
-
After register allocation and post-register allocation instruction splitting, perform a copy-propagation pass to try to reduce scheduling dependencies and occasionally eliminate the copy.
Enabled at levels -O, -O2, -O3, -Os.
-
-fprofile-correction
-
Profiles collected using an instrumented binary for multi-threaded programs may be inconsistent due to missed counter updates. When this option is specified, GCC uses heuristics to correct or smooth out such inconsistencies. By default, GCC emits an error message when an inconsistent profile is detected.
-
-fprofile-dir=path
-
Set the directory to search for the profile data files in to path. This option affects only the profile data generated by -fprofile-generate, -ftest-coverage, -fprofile-arcs and used by -fprofile-use and -fbranch-probabilities and its related options. Both absolute and relative paths can be used. By default, GCC uses the current directory as path, thus the profile data file appears in the same directory as the object file.
-
-fprofile-generate
-
-
-fprofile-generate=path
-
Enable options usually used for instrumenting application to produce profile useful for later recompilation with profile feedback based optimization. You must use -fprofile-generate both when compiling and when linking your program.
The following options are enabled: "-fprofile-arcs", "-fprofile-values", "-fvpt".
If path is specified, GCC looks at the path to find the profile feedback data files. See -fprofile-dir.
-
-fprofile-use
-
-
-fprofile-use=path
-
Enable profile feedback directed optimizations, and optimizations generally profitable only with profile feedback available.
The following options are enabled: "-fbranch-probabilities", "-fvpt", "-funroll-loops", "-fpeel-loops", "-ftracer", "-ftree-vectorize", "ftree-loop-distribute-patterns"
By default, GCC emits an error message if the feedback profiles do not match the source code. This error can be turned into a warning by using -Wcoverage-mismatch. Note this may result in poorly optimized code.
If path is specified, GCC looks at the path to find the profile feedback data files. See -fprofile-dir.
The following options control compiler behavior regarding floating-point arithmetic. These options trade off between speed and correctness. All must be specifically enabled.
-
-ffloat-store
-
Do not store floating-point variables in registers, and inhibit other options that might change whether a floating-point value is taken from a register or memory.
This option prevents undesirable excess precision on machines such as the 68000 where the floating registers (of the 68881) keep more precision than a "double" is supposed to have. Similarly for the x86 architecture. For most programs, the excess precision does only good, but a few programs rely on the precise definition of IEEE floating point. Use -ffloat-store for such programs, after modifying them to store all pertinent intermediate computations into variables.
-
-fexcess-precision=style
-
This option allows further control over excess precision on machines where floating-point registers have more precision than the IEEE "float" and "double" types and the processor does not support operations rounding to those types. By default, -fexcess-precision=fast is in effect; this means that operations are carried out in the precision of the registers and that it is unpredictable when rounding to the types specified in the source code takes place. When compiling C, if -fexcess-precision=standard is specified then excess precision follows the rules specified in ISO C99; in particular, both casts and assignments cause values to be rounded to their semantic types (whereas -ffloat-store only affects assignments). This option is enabled by default for C if a strict conformance option such as -std=c99 is used.
-fexcess-precision=standard is not implemented for languages other than C, and has no effect if -funsafe-math-optimizations or -ffast-math is specified. On the x86, it also has no effect if -mfpmath=sse or -mfpmath=sse+387 is specified; in the former case, IEEE semantics apply without excess precision, and in the latter, rounding is unpredictable.
-
-ffast-math
-
Sets -fno-math-errno, -funsafe-math-optimizations, -ffinite-math-only, -fno-rounding-math, -fno-signaling-nans and -fcx-limited-range.
This option causes the preprocessor macro "__FAST_MATH__" to be defined.
This option is not turned on by any -O option besides -Ofast since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications.
-
-fno-math-errno
-
Do not set "errno" after calling math functions that are executed with a single instruction, e.g., "sqrt". A program that relies on IEEE exceptions for math error handling may want to use this flag for speed while maintaining IEEE arithmetic compatibility.
This option is not turned on by any -O option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications.
The default is -fmath-errno.
On Darwin systems, the math library never sets "errno". There is therefore no reason for the compiler to consider the possibility that it might, and -fno-math-errno is the default.
-
-funsafe-math-optimizations
-
Allow optimizations for floating-point arithmetic that (a) assume that arguments and results are valid and (b) may violate IEEE or ANSI standards. When used at link-time, it may include libraries or startup files that change the default FPU control word or other similar optimizations.
This option is not turned on by any -O option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. Enables -fno-signed-zeros, -fno-trapping-math, -fassociative-math and -freciprocal-math.
The default is -fno-unsafe-math-optimizations.
-
-fassociative-math
-
Allow re-association of operands in series of floating-point operations. This violates the ISO C and C++ language standard by possibly changing computation result. NOTE: re-ordering may change the sign of zero as well as ignore NaNs and inhibit or create underflow or overflow (and thus cannot be used on code that relies on rounding behavior like "(x + 2**52) - 2**52". May also reorder floating-point comparisons and thus may not be used when ordered comparisons are required. This option requires that both -fno-signed-zeros and -fno-trapping-math be in effect. Moreover, it doesn't make much sense with -frounding-math. For Fortran the option is automatically enabled when both -fno-signed-zeros and -fno-trapping-math are in effect.
The default is -fno-associative-math.
-
-freciprocal-math
-
Allow the reciprocal of a value to be used instead of dividing by the value if this enables optimizations. For example "x / y" can be replaced with "x * (1/y)", which is useful if "(1/y)" is subject to common subexpression elimination. Note that this loses precision and increases the number of flops operating on the value.
The default is -fno-reciprocal-math.
-
-ffinite-math-only
-
Allow optimizations for floating-point arithmetic that assume that arguments and results are not NaNs or +-Infs.
This option is not turned on by any -O option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications.
The default is -fno-finite-math-only.
-
-fno-signed-zeros
-
Allow optimizations for floating-point arithmetic that ignore the signedness of zero. IEEE arithmetic specifies the behavior of distinct +0.0 and -0.0 values, which then prohibits simplification of expressions such as x+0.0 or 0.0*x (even with -ffinite-math-only). This option implies that the sign of a zero result isn't significant.
The default is -fsigned-zeros.
-
-fno-trapping-math
-
Compile code assuming that floating-point operations cannot generate user-visible traps. These traps include division by zero, overflow, underflow, inexact result and invalid operation. This option requires that -fno-signaling-nans be in effect. Setting this option may allow faster code if one relies on "non-stop" IEEE arithmetic, for example.
This option should never be turned on by any -O option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math functions.
The default is -ftrapping-math.
-
-frounding-math
-
Disable transformations and optimizations that assume default floating-point rounding behavior. This is round-to-zero for all floating point to integer conversions, and round-to-nearest for all other arithmetic truncations. This option should be specified for programs that change the FP rounding mode dynamically, or that may be executed with a non-default rounding mode. This option disables constant folding of floating-point expressions at compile time (which may be affected by rounding mode) and arithmetic transformations that are unsafe in the presence of sign-dependent rounding modes.
The default is -fno-rounding-math.
This option is experimental and does not currently guarantee to disable all GCC optimizations that are affected by rounding mode. Future versions of GCC may provide finer control of this setting using C99's "FENV_ACCESS" pragma. This command-line option will be used to specify the default state for "FENV_ACCESS".
-
-fsignaling-nans
-
Compile code assuming that IEEE signaling NaNs may generate user-visible traps during floating-point operations. Setting this option disables optimizations that may change the number of exceptions visible with signaling NaNs. This option implies -ftrapping-math.
This option causes the preprocessor macro "__SUPPORT_SNAN__" to be defined.
The default is -fno-signaling-nans.
This option is experimental and does not currently guarantee to disable all GCC optimizations that affect signaling NaN behavior.
-
-fsingle-precision-constant
-
Treat floating-point constants as single precision instead of implicitly converting them to double-precision constants.
-
-fcx-limited-range
-
When enabled, this option states that a range reduction step is not needed when performing complex division. Also, there is no checking whether the result of a complex multiplication or division is "NaN + I*NaN", with an attempt to rescue the situation in that case. The default is -fno-cx-limited-range, but is enabled by -ffast-math.
This option controls the default setting of the ISO C99 "CX_LIMITED_RANGE" pragma. Nevertheless, the option applies to all languages.
-
-fcx-fortran-rules
-
Complex multiplication and division follow Fortran rules. Range reduction is done as part of complex division, but there is no checking whether the result of a complex multiplication or division is "NaN + I*NaN", with an attempt to rescue the situation in that case.
The default is -fno-cx-fortran-rules.
The following options control optimizations that may improve performance, but are not enabled by any -O options. This section includes experimental options that may produce broken code.
-
-fbranch-probabilities
-
After running a program compiled with -fprofile-arcs, you can compile it a second time using -fbranch-probabilities, to improve optimizations based on the number of times each branch was taken. When a program compiled with -fprofile-arcs exits, it saves arc execution counts to a file called sourcename.gcda for each source file. The information in this data file is very dependent on the structure of the generated code, so you must use the same source code and the same optimization options for both compilations.
With -fbranch-probabilities, GCC puts a REG_BR_PROB note on each JUMP_INSN and CALL_INSN. These can be used to improve optimization. Currently, they are only used in one place: in reorg.c, instead of guessing which path a branch is most likely to take, the REG_BR_PROB values are used to exactly determine which path is taken more often.
-
-fprofile-values
-
If combined with -fprofile-arcs, it adds code so that some data about values of expressions in the program is gathered.
With -fbranch-probabilities, it reads back the data gathered from profiling values of expressions for usage in optimizations.
Enabled with -fprofile-generate and -fprofile-use.
-
-fvpt
-
If combined with -fprofile-arcs, this option instructs the compiler to add code to gather information about values of expressions.
With -fbranch-probabilities, it reads back the data gathered and actually performs the optimizations based on them. Currently the optimizations include specialization of division operations using the knowledge about the value of the denominator.
-
-frename-registers
-
Attempt to avoid false dependencies in scheduled code by making use of registers left over after register allocation. This optimization most benefits processors with lots of registers. Depending on the debug information format adopted by the target, however, it can make debugging impossible, since variables no longer stay in a "home register".
Enabled by default with -funroll-loops and -fpeel-loops.
-
-ftracer
-
Perform tail duplication to enlarge superblock size. This transformation simplifies the control flow of the function allowing other optimizations to do a better job.
Enabled with -fprofile-use.
-
-funroll-loops
-
Unroll loops whose number of iterations can be determined at compile time or upon entry to the loop. -funroll-loops implies -frerun-cse-after-loop, -fweb and -frename-registers. It also turns on complete loop peeling (i.e. complete removal of loops with a small constant number of iterations). This option makes code larger, and may or may not make it run faster.
Enabled with -fprofile-use.
-
-funroll-all-loops
-
Unroll all loops, even if their number of iterations is uncertain when the loop is entered. This usually makes programs run more slowly. -funroll-all-loops implies the same options as -funroll-loops.
-
-fpeel-loops
-
Peels loops for which there is enough information that they do not roll much (from profile feedback). It also turns on complete loop peeling (i.e. complete removal of loops with small constant number of iterations).
Enabled with -fprofile-use.
-
-fmove-loop-invariants
-
Enables the loop invariant motion pass in the RTL loop optimizer. Enabled at level -O1
-
-funswitch-loops
-
Move branches with loop invariant conditions out of the loop, with duplicates of the loop on both branches (modified according to result of the condition).
-
-ffunction-sections
-
-
-fdata-sections
-
Place each function or data item into its own section in the output file if the target supports arbitrary sections. The name of the function or the name of the data item determines the section's name in the output file.
Use these options on systems where the linker can perform optimizations to improve locality of reference in the instruction space. Most systems using the ELF object format and SPARC processors running Solaris 2 have linkers with such optimizations. AIX may have these optimizations in the future.
Only use these options when there are significant benefits from doing so. When you specify these options, the assembler and linker create larger object and executable files and are also slower. You cannot use "gprof" on all systems if you specify this option, and you may have problems with debugging if you specify both this option and -g.
-
-fbranch-target-load-optimize
-
Perform branch target register load optimization before prologue / epilogue threading. The use of target registers can typically be exposed only during reload, thus hoisting loads out of loops and doing inter-block scheduling needs a separate optimization pass.
-
-fbranch-target-load-optimize2
-
Perform branch target register load optimization after prologue / epilogue threading.
-
-fbtr-bb-exclusive
-
When performing branch target register load optimization, don't reuse branch target registers within any basic block.
-
-fstack-protector
-
Emit extra code to check for buffer overflows, such as stack smashing attacks. This is done by adding a guard variable to functions with vulnerable objects. This includes functions that call "alloca", and functions with buffers larger than 8 bytes. The guards are initialized when a function is entered and then checked when the function exits. If a guard check fails, an error message is printed and the program exits.
-
-fstack-protector-all
-
Like -fstack-protector except that all functions are protected.
-
-fsection-anchors
-
Try to reduce the number of symbolic address calculations by using shared "anchor" symbols to address nearby objects. This transformation can help to reduce the number of GOT entries and GOT accesses on some targets.
For example, the implementation of the following function "foo":
static int a, b, c;
int foo (void) { return a + b + c; }
usually calculates the addresses of all three variables, but if you compile it with -fsection-anchors, it accesses the variables from a common anchor point instead. The effect is similar to the following pseudocode (which isn't valid C):
int foo (void)
{
register int *xr = &x;
return xr[&a - &x] + xr[&b - &x] + xr[&c - &x];
}
Not all targets support this option.
-
--param name=value
-
In some places, GCC uses various constants to control the amount of optimization that is done. For example, GCC does not inline functions that contain more than a certain number of instructions. You can control some of these constants on the command line using the --param option.
The names of specific parameters, and the meaning of the values, are tied to the internals of the compiler, and are subject to change without notice in future releases.
In each case, the value is an integer. The allowable choices for name are:
-
predictable-branch-outcome
-
When branch is predicted to be taken with probability lower than this threshold (in percent), then it is considered well predictable. The default is 10.
-
max-crossjump-edges
-
The maximum number of incoming edges to consider for cross-jumping. The algorithm used by -fcrossjumping is O(N^2) in the number of edges incoming to each block. Increasing values mean more aggressive optimization, making the compilation time increase with probably small improvement in executable size.
-
min-crossjump-insns
-
The minimum number of instructions that must be matched at the end of two blocks before cross-jumping is performed on them. This value is ignored in the case where all instructions in the block being cross-jumped from are matched. The default value is 5.
-
max-grow-copy-bb-insns
-
The maximum code size expansion factor when copying basic blocks instead of jumping. The expansion is relative to a jump instruction. The default value is 8.
-
max-goto-duplication-insns
-
The maximum number of instructions to duplicate to a block that jumps to a computed goto. To avoid O(N^2) behavior in a number of passes, GCC factors computed gotos early in the compilation process, and unfactors them as late as possible. Only computed jumps at the end of a basic blocks with no more than max-goto-duplication-insns are unfactored. The default value is 8.
-
max-delay-slot-insn-search
-
The maximum number of instructions to consider when looking for an instruction to fill a delay slot. If more than this arbitrary number of instructions are searched, the time savings from filling the delay slot are minimal, so stop searching. Increasing values mean more aggressive optimization, making the compilation time increase with probably small improvement in execution time.
-
max-delay-slot-live-search
-
When trying to fill delay slots, the maximum number of instructions to consider when searching for a block with valid live register information. Increasing this arbitrarily chosen value means more aggressive optimization, increasing the compilation time. This parameter should be removed when the delay slot code is rewritten to maintain the control-flow graph.
-
max-gcse-memory
-
The approximate maximum amount of memory that can be allocated in order to perform the global common subexpression elimination optimization. If more memory than specified is required, the optimization is not done.
-
max-gcse-insertion-ratio
-
If the ratio of expression insertions to deletions is larger than this value for any expression, then RTL PRE inserts or removes the expression and thus leaves partially redundant computations in the instruction stream. The default value is 20.
-
max-pending-list-length
-
The maximum number of pending dependencies scheduling allows before flushing the current state and starting over. Large functions with few branches or calls can create excessively large lists which needlessly consume memory and resources.
-
max-modulo-backtrack-attempts
-
The maximum number of backtrack attempts the scheduler should make when modulo scheduling a loop. Larger values can exponentially increase compilation time.
-
max-inline-insns-single
-
Several parameters control the tree inliner used in GCC. This number sets the maximum number of instructions (counted in GCC's internal representation) in a single function that the tree inliner considers for inlining. This only affects functions declared inline and methods implemented in a class declaration (C++). The default value is 400.
-
max-inline-insns-auto
-
When you use -finline-functions (included in -O3), a lot of functions that would otherwise not be considered for inlining by the compiler are investigated. To those functions, a different (more restrictive) limit compared to functions declared inline can be applied. The default value is 40.
-
inline-min-speedup
-
When estimated performance improvement of caller + callee runtime exceeds this threshold (in precent), the function can be inlined regardless the limit on --param max-inline-insns-single and --param max-inline-insns-auto.
-
large-function-insns
-
The limit specifying really large functions. For functions larger than this limit after inlining, inlining is constrained by --param large-function-growth. This parameter is useful primarily to avoid extreme compilation time caused by non-linear algorithms used by the back end. The default value is 2700.
-
large-function-growth
-
Specifies maximal growth of large function caused by inlining in percents. The default value is 100 which limits large function growth to 2.0 times the original size.
-
large-unit-insns
-
The limit specifying large translation unit. Growth caused by inlining of units larger than this limit is limited by --param inline-unit-growth. For small units this might be too tight. For example, consider a unit consisting of function A that is inline and B that just calls A three times. If B is small relative to A, the growth of unit is 300\% and yet such inlining is very sane. For very large units consisting of small inlineable functions, however, the overall unit growth limit is needed to avoid exponential explosion of code size. Thus for smaller units, the size is increased to --param large-unit-insns before applying --param inline-unit-growth. The default is 10000.
-
inline-unit-growth
-
Specifies maximal overall growth of the compilation unit caused by inlining. The default value is 30 which limits unit growth to 1.3 times the original size.
-
ipcp-unit-growth
-
Specifies maximal overall growth of the compilation unit caused by interprocedural constant propagation. The default value is 10 which limits unit growth to 1.1 times the original size.
-
large-stack-frame
-
The limit specifying large stack frames. While inlining the algorithm is trying to not grow past this limit too much. The default value is 256 bytes.
-
large-stack-frame-growth
-
Specifies maximal growth of large stack frames caused by inlining in percents. The default value is 1000 which limits large stack frame growth to 11 times the original size.
-
max-inline-insns-recursive
-
-
max-inline-insns-recursive-auto
-
Specifies the maximum number of instructions an out-of-line copy of a self-recursive inline function can grow into by performing recursive inlining.
For functions declared inline, --param max-inline-insns-recursive is taken into account. For functions not declared inline, recursive inlining happens only when -finline-functions (included in -O3) is enabled and --param max-inline-insns-recursive-auto is used. The default value is 450.
-
max-inline-recursive-depth
-
-
max-inline-recursive-depth-auto
-
Specifies the maximum recursion depth used for recursive inlining.
For functions declared inline, --param max-inline-recursive-depth is taken into account. For functions not declared inline, recursive inlining happens only when -finline-functions (included in -O3) is enabled and --param max-inline-recursive-depth-auto is used. The default value is 8.
-
min-inline-recursive-probability
-
Recursive inlining is profitable only for function having deep recursion in average and can hurt for function having little recursion depth by increasing the prologue size or complexity of function body to other optimizers.
When profile feedback is available (see -fprofile-generate) the actual recursion depth can be guessed from probability that function recurses via a given call expression. This parameter limits inlining only to call expressions whose probability exceeds the given threshold (in percents). The default value is 10.
-
early-inlining-insns
-
Specify growth that the early inliner can make. In effect it increases the amount of inlining for code having a large abstraction penalty. The default value is 10.
-
max-early-inliner-iterations
-
-
max-early-inliner-iterations
-
Limit of iterations of the early inliner. This basically bounds the number of nested indirect calls the early inliner can resolve. Deeper chains are still handled by late inlining.
-
comdat-sharing-probability
-
-
comdat-sharing-probability
-
Probability (in percent) that C++ inline function with comdat visibility are shared across multiple compilation units. The default value is 20.
-
min-vect-loop-bound
-
The minimum number of iterations under which loops are not vectorized when -ftree-vectorize is used. The number of iterations after vectorization needs to be greater than the value specified by this option to allow vectorization. The default value is 0.
-
gcse-cost-distance-ratio
-
Scaling factor in calculation of maximum distance an expression can be moved by GCSE optimizations. This is currently supported only in the code hoisting pass. The bigger the ratio, the more aggressive code hoisting is with simple expressions, i.e., the expressions that have cost less than gcse-unrestricted-cost. Specifying 0 disables hoisting of simple expressions. The default value is 10.
-
gcse-unrestricted-cost
-
Cost, roughly measured as the cost of a single typical machine instruction, at which GCSE optimizations do not constrain the distance an expression can travel. This is currently supported only in the code hoisting pass. The lesser the cost, the more aggressive code hoisting is. Specifying 0 allows all expressions to travel unrestricted distances. The default value is 3.
-
max-hoist-depth
-
The depth of search in the dominator tree for expressions to hoist. This is used to avoid quadratic behavior in hoisting algorithm. The value of 0 does not limit on the search, but may slow down compilation of huge functions. The default value is 30.
-
max-tail-merge-comparisons
-
The maximum amount of similar bbs to compare a bb with. This is used to avoid quadratic behavior in tree tail merging. The default value is 10.
-
max-tail-merge-iterations
-
The maximum amount of iterations of the pass over the function. This is used to limit compilation time in tree tail merging. The default value is 2.
-
max-unrolled-insns
-
The maximum number of instructions that a loop may have to be unrolled. If a loop is unrolled, this parameter also determines how many times the loop code is unrolled.
-
max-average-unrolled-insns
-
The maximum number of instructions biased by probabilities of their execution that a loop may have to be unrolled. If a loop is unrolled, this parameter also determines how many times the loop code is unrolled.
-
max-unroll-times
-
The maximum number of unrollings of a single loop.
-
max-peeled-insns
-
The maximum number of instructions that a loop may have to be peeled. If a loop is peeled, this parameter also determines how many times the loop code is peeled.
-
max-peel-times
-
The maximum number of peelings of a single loop.
-
max-peel-branches
-
The maximum number of branches on the hot path through the peeled sequence.
-
max-completely-peeled-insns
-
The maximum number of insns of a completely peeled loop.
-
max-completely-peel-times
-
The maximum number of iterations of a loop to be suitable for complete peeling.
-
max-completely-peel-loop-nest-depth
-
The maximum depth of a loop nest suitable for complete peeling.
-
max-unswitch-insns
-
The maximum number of insns of an unswitched loop.
-
max-unswitch-level
-
The maximum number of branches unswitched in a single loop.
-
lim-expensive
-
The minimum cost of an expensive expression in the loop invariant motion.
-
iv-consider-all-candidates-bound
-
Bound on number of candidates for induction variables, below which all candidates are considered for each use in induction variable optimizations. If there are more candidates than this, only the most relevant ones are considered to avoid quadratic time complexity.
-
iv-max-considered-uses
-
The induction variable optimizations give up on loops that contain more induction variable uses.
-
iv-always-prune-cand-set-bound
-
If the number of candidates in the set is smaller than this value, always try to remove unnecessary ivs from the set when adding a new one.
-
scev-max-expr-size
-
Bound on size of expressions used in the scalar evolutions analyzer. Large expressions slow the analyzer.
-
scev-max-expr-complexity
-
Bound on the complexity of the expressions in the scalar evolutions analyzer. Complex expressions slow the analyzer.
-
omega-max-vars
-
The maximum number of variables in an Omega constraint system. The default value is 128.
-
omega-max-geqs
-
The maximum number of inequalities in an Omega constraint system. The default value is 256.
-
omega-max-eqs
-
The maximum number of equalities in an Omega constraint system. The default value is 128.
-
omega-max-wild-cards
-
The maximum number of wildcard variables that the Omega solver is able to insert. The default value is 18.
-
omega-hash-table-size
-
The size of the hash table in the Omega solver. The default value is 550.
-
omega-max-keys
-
The maximal number of keys used by the Omega solver. The default value is 500.
-
omega-eliminate-redundant-constraints
-
When set to 1, use expensive methods to eliminate all redundant constraints. The default value is 0.
-
vect-max-version-for-alignment-checks
-
The maximum number of run-time checks that can be performed when doing loop versioning for alignment in the vectorizer. See option -ftree-vect-loop-version for more information.
-
vect-max-version-for-alias-checks
-
The maximum number of run-time checks that can be performed when doing loop versioning for alias in the vectorizer. See option -ftree-vect-loop-version for more information.
-
max-iterations-to-track
-
The maximum number of iterations of a loop the brute-force algorithm for analysis of the number of iterations of the loop tries to evaluate.
-
hot-bb-count-ws-permille
-
A basic block profile count is considered hot if it contributes to the given permillage (i.e. 0...1000) of the entire profiled execution.
-
hot-bb-frequency-fraction
-
Select fraction of the entry block frequency of executions of basic block in function given basic block needs to have to be considered hot.
-
max-predicted-iterations
-
The maximum number of loop iterations we predict statically. This is useful in cases where a function contains a single loop with known bound and another loop with unknown bound. The known number of iterations is predicted correctly, while the unknown number of iterations average to roughly 10. This means that the loop without bounds appears artificially cold relative to the other one.
-
align-threshold
-
Select fraction of the maximal frequency of executions of a basic block in a function to align the basic block.
-
align-loop-iterations
-
A loop expected to iterate at least the selected number of iterations is aligned.
-
tracer-dynamic-coverage
-
-
tracer-dynamic-coverage-feedback
-
This value is used to limit superblock formation once the given percentage of executed instructions is covered. This limits unnecessary code size expansion.
The tracer-dynamic-coverage-feedback is used only when profile feedback is available. The real profiles (as opposed to statically estimated ones) are much less balanced allowing the threshold to be larger value.
-
tracer-max-code-growth
-
Stop tail duplication once code growth has reached given percentage. This is a rather artificial limit, as most of the duplicates are eliminated later in cross jumping, so it may be set to much higher values than is the desired code growth.
-
tracer-min-branch-ratio
-
Stop reverse growth when the reverse probability of best edge is less than this threshold (in percent).
-
tracer-min-branch-ratio
-
-
tracer-min-branch-ratio-feedback
-
Stop forward growth if the best edge has probability lower than this threshold.
Similarly to tracer-dynamic-coverage two values are present, one for compilation for profile feedback and one for compilation without. The value for compilation with profile feedback needs to be more conservative (higher) in order to make tracer effective.
-
max-cse-path-length
-
The maximum number of basic blocks on path that CSE considers. The default is 10.
-
max-cse-insns
-
The maximum number of instructions CSE processes before flushing. The default is 1000.
-
ggc-min-expand
-
GCC uses a garbage collector to manage its own memory allocation. This parameter specifies the minimum percentage by which the garbage collector's heap should be allowed to expand between collections. Tuning this may improve compilation speed; it has no effect on code generation.
The default is 30% + 70% * (RAM/1GB) with an upper bound of 100% when RAM >= 1GB. If "getrlimit" is available, the notion of "RAM" is the smallest of actual RAM and "RLIMIT_DATA" or "RLIMIT_AS". If GCC is not able to calculate RAM on a particular platform, the lower bound of 30% is used. Setting this parameter and ggc-min-heapsize to zero causes a full collection to occur at every opportunity. This is extremely slow, but can be useful for debugging.
-
ggc-min-heapsize
-
Minimum size of the garbage collector's heap before it begins bothering to collect garbage. The first collection occurs after the heap expands by ggc-min-expand% beyond ggc-min-heapsize. Again, tuning this may improve compilation speed, and has no effect on code generation.
The default is the smaller of RAM/8, RLIMIT_RSS, or a limit that tries to ensure that RLIMIT_DATA or RLIMIT_AS are not exceeded, but with a lower bound of 4096 (four megabytes) and an upper bound of 131072 (128 megabytes). If GCC is not able to calculate RAM on a particular platform, the lower bound is used. Setting this parameter very large effectively disables garbage collection. Setting this parameter and ggc-min-expand to zero causes a full collection to occur at every opportunity.
-
max-reload-search-insns
-
The maximum number of instruction reload should look backward for equivalent register. Increasing values mean more aggressive optimization, making the compilation time increase with probably slightly better performance. The default value is 100.
-
max-cselib-memory-locations
-
The maximum number of memory locations cselib should take into account. Increasing values mean more aggressive optimization, making the compilation time increase with probably slightly better performance. The default value is 500.
-
reorder-blocks-duplicate
-
-
reorder-blocks-duplicate-feedback
-
Used by the basic block reordering pass to decide whether to use unconditional branch or duplicate the code on its destination. Code is duplicated when its estimated size is smaller than this value multiplied by the estimated size of unconditional jump in the hot spots of the program.
The reorder-block-duplicate-feedback is used only when profile feedback is available. It may be set to higher values than reorder-block-duplicate since information about the hot spots is more accurate.
-
max-sched-ready-insns
-
The maximum number of instructions ready to be issued the scheduler should consider at any given time during the first scheduling pass. Increasing values mean more thorough searches, making the compilation time increase with probably little benefit. The default value is 100.
-
max-sched-region-blocks
-
The maximum number of blocks in a region to be considered for interblock scheduling. The default value is 10.
-
max-pipeline-region-blocks
-
The maximum number of blocks in a region to be considered for pipelining in the selective scheduler. The default value is 15.
-
max-sched-region-insns
-
The maximum number of insns in a region to be considered for interblock scheduling. The default value is 100.
-
max-pipeline-region-insns
-
The maximum number of insns in a region to be considered for pipelining in the selective scheduler. The default value is 200.
-
min-spec-prob
-
The minimum probability (in percents) of reaching a source block for interblock speculative scheduling. The default value is 40.
-
max-sched-extend-regions-iters
-
The maximum number of iterations through CFG to extend regions. A value of 0 (the default) disables region extensions.
-
max-sched-insn-conflict-delay
-
The maximum conflict delay for an insn to be considered for speculative motion. The default value is 3.
-
sched-spec-prob-cutoff
-
The minimal probability of speculation success (in percents), so that speculative insns are scheduled. The default value is 40.
-
sched-spec-state-edge-prob-cutoff
-
The minimum probability an edge must have for the scheduler to save its state across it. The default value is 10.
-
sched-mem-true-dep-cost
-
Minimal distance (in CPU cycles) between store and load targeting same memory locations. The default value is 1.
-
selsched-max-lookahead
-
The maximum size of the lookahead window of selective scheduling. It is a depth of search for available instructions. The default value is 50.
-
selsched-max-sched-times
-
The maximum number of times that an instruction is scheduled during selective scheduling. This is the limit on the number of iterations through which the instruction may be pipelined. The default value is 2.
-
selsched-max-insns-to-rename
-
The maximum number of best instructions in the ready list that are considered for renaming in the selective scheduler. The default value is 2.
-
sms-min-sc
-
The minimum value of stage count that swing modulo scheduler generates. The default value is 2.
-
max-last-value-rtl
-
The maximum size measured as number of RTLs that can be recorded in an expression in combiner for a pseudo register as last known value of that register. The default is 10000.
-
integer-share-limit
-
Small integer constants can use a shared data structure, reducing the compiler's memory usage and increasing its speed. This sets the maximum value of a shared integer constant. The default value is 256.
-
ssp-buffer-size
-
The minimum size of buffers (i.e. arrays) that receive stack smashing protection when -fstack-protection is used.
-
max-jump-thread-duplication-stmts
-
Maximum number of statements allowed in a block that needs to be duplicated when threading jumps.
-
max-fields-for-field-sensitive
-
Maximum number of fields in a structure treated in a field sensitive manner during pointer analysis. The default is zero for -O0 and -O1, and 100 for -Os, -O2, and -O3.
-
prefetch-latency
-
Estimate on average number of instructions that are executed before prefetch finishes. The distance prefetched ahead is proportional to this constant. Increasing this number may also lead to less streams being prefetched (see simultaneous-prefetches).
-
simultaneous-prefetches
-
Maximum number of prefetches that can run at the same time.
-
l1-cache-line-size
-
The size of cache line in L1 cache, in bytes.
-
l1-cache-size
-
The size of L1 cache, in kilobytes.
-
l2-cache-size
-
The size of L2 cache, in kilobytes.
-
min-insn-to-prefetch-ratio
-
The minimum ratio between the number of instructions and the number of prefetches to enable prefetching in a loop.
-
prefetch-min-insn-to-mem-ratio
-
The minimum ratio between the number of instructions and the number of memory references to enable prefetching in a loop.
-
use-canonical-types
-
Whether the compiler should use the "canonical" type system. By default, this should always be 1, which uses a more efficient internal mechanism for comparing types in C++ and Objective-C++. However, if bugs in the canonical type system are causing compilation failures, set this value to 0 to disable canonical types.
-
switch-conversion-max-branch-ratio
-
Switch initialization conversion refuses to create arrays that are bigger than switch-conversion-max-branch-ratio times the number of branches in the switch.
-
max-partial-antic-length
-
Maximum length of the partial antic set computed during the tree partial redundancy elimination optimization ( -ftree-pre) when optimizing at -O3 and above. For some sorts of source code the enhanced partial redundancy elimination optimization can run away, consuming all of the memory available on the host machine. This parameter sets a limit on the length of the sets that are computed, which prevents the runaway behavior. Setting a value of 0 for this parameter allows an unlimited set length.
-
sccvn-max-scc-size
-
Maximum size of a strongly connected component (SCC) during SCCVN processing. If this limit is hit, SCCVN processing for the whole function is not done and optimizations depending on it are disabled. The default maximum SCC size is 10000.
-
sccvn-max-alias-queries-per-access
-
Maximum number of alias-oracle queries we perform when looking for redundancies for loads and stores. If this limit is hit the search is aborted and the load or store is not considered redundant. The number of queries is algorithmically limited to the number of stores on all paths from the load to the function entry. The default maxmimum number of queries is 1000.
-
ira-max-loops-num
-
IRA uses regional register allocation by default. If a function contains more loops than the number given by this parameter, only at most the given number of the most frequently-executed loops form regions for regional register allocation. The default value of the parameter is 100.
-
ira-max-conflict-table-size
-
Although IRA uses a sophisticated algorithm to compress the conflict table, the table can still require excessive amounts of memory for huge functions. If the conflict table for a function could be more than the size in MB given by this parameter, the register allocator instead uses a faster, simpler, and lower-quality algorithm that does not require building a pseudo-register conflict table. The default value of the parameter is 2000.
-
ira-loop-reserved-regs
-
IRA can be used to evaluate more accurate register pressure in loops for decisions to move loop invariants (see -O3). The number of available registers reserved for some other purposes is given by this parameter. The default value of the parameter is 2, which is the minimal number of registers needed by typical instructions. This value is the best found from numerous experiments.
-
loop-invariant-max-bbs-in-loop
-
Loop invariant motion can be very expensive, both in compilation time and in amount of needed compile-time memory, with very large loops. Loops with more basic blocks than this parameter won't have loop invariant motion optimization performed on them. The default value of the parameter is 1000 for -O1 and 10000 for -O2 and above.
-
loop-max-datarefs-for-datadeps
-
Building data dapendencies is expensive for very large loops. This parameter limits the number of data references in loops that are considered for data dependence analysis. These large loops are no handled by the optimizations using loop data dependencies. The default value is 1000.
-
max-vartrack-size
-
Sets a maximum number of hash table slots to use during variable tracking dataflow analysis of any function. If this limit is exceeded with variable tracking at assignments enabled, analysis for that function is retried without it, after removing all debug insns from the function. If the limit is exceeded even without debug insns, var tracking analysis is completely disabled for the function. Setting the parameter to zero makes it unlimited.
-
max-vartrack-expr-depth
-
Sets a maximum number of recursion levels when attempting to map variable names or debug temporaries to value expressions. This trades compilation time for more complete debug information. If this is set too low, value expressions that are available and could be represented in debug information may end up not being used; setting this higher may enable the compiler to find more complex debug expressions, but compile time and memory use may grow. The default is 12.
-
min-nondebug-insn-uid
-
Use uids starting at this parameter for nondebug insns. The range below the parameter is reserved exclusively for debug insns created by -fvar-tracking-assignments, but debug insns may get (non-overlapping) uids above it if the reserved range is exhausted.
-
ipa-sra-ptr-growth-factor
-
IPA-SRA replaces a pointer to an aggregate with one or more new parameters only when their cumulative size is less or equal to ipa-sra-ptr-growth-factor times the size of the original pointer parameter.
-
tm-max-aggregate-size
-
When making copies of thread-local variables in a transaction, this parameter specifies the size in bytes after which variables are saved with the logging functions as opposed to save/restore code sequence pairs. This option only applies when using -fgnu-tm.
-
graphite-max-nb-scop-params
-
To avoid exponential effects in the Graphite loop transforms, the number of parameters in a Static Control Part (SCoP) is bounded. The default value is 10 parameters. A variable whose value is unknown at compilation time and defined outside a SCoP is a parameter of the SCoP.
-
graphite-max-bbs-per-function
-
To avoid exponential effects in the detection of SCoPs, the size of the functions analyzed by Graphite is bounded. The default value is 100 basic blocks.
-
loop-block-tile-size
-
Loop blocking or strip mining transforms, enabled with -floop-block or -floop-strip-mine, strip mine each loop in the loop nest by a given number of iterations. The strip length can be changed using the loop-block-tile-size parameter. The default value is 51 iterations.
-
ipa-cp-value-list-size
-
IPA-CP attempts to track all possible values and types passed to a function's parameter in order to propagate them and perform devirtualization. ipa-cp-value-list-size is the maximum number of values and types it stores per one formal parameter of a function.
-
lto-partitions
-
Specify desired number of partitions produced during WHOPR compilation. The number of partitions should exceed the number of CPUs used for compilation. The default value is 32.
-
lto-minpartition
-
Size of minimal partition for WHOPR (in estimated instructions). This prevents expenses of splitting very small programs into too many partitions.
-
cxx-max-namespaces-for-diagnostic-help
-
The maximum number of namespaces to consult for suggestions when C++ name lookup fails for an identifier. The default is 1000.
-
sink-frequency-threshold
-
The maximum relative execution frequency (in percents) of the target block relative to a statement's original block to allow statement sinking of a statement. Larger numbers result in more aggressive statement sinking. The default value is 75. A small positive adjustment is applied for statements with memory operands as those are even more profitable so sink.
-
max-stores-to-sink
-
The maximum number of conditional stores paires that can be sunk. Set to 0 if either vectorization ( -ftree-vectorize) or if-conversion ( -ftree-loop-if-convert) is disabled. The default is 2.
-
allow-load-data-races
-
Allow optimizers to introduce new data races on loads. Set to 1 to allow, otherwise to 0. This option is enabled by default unless implicitly set by the -fmemory-model= option.
-
allow-store-data-races
-
Allow optimizers to introduce new data races on stores. Set to 1 to allow, otherwise to 0. This option is enabled by default unless implicitly set by the -fmemory-model= option.
-
allow-packed-load-data-races
-
Allow optimizers to introduce new data races on packed data loads. Set to 1 to allow, otherwise to 0. This option is enabled by default unless implicitly set by the -fmemory-model= option.
-
allow-packed-store-data-races
-
Allow optimizers to introduce new data races on packed data stores. Set to 1 to allow, otherwise to 0. This option is enabled by default unless implicitly set by the -fmemory-model= option.
-
case-values-threshold
-
The smallest number of different values for which it is best to use a jump-table instead of a tree of conditional branches. If the value is 0, use the default for the machine. The default is 0.
-
tree-reassoc-width
-
Set the maximum number of instructions executed in parallel in reassociated tree. This parameter overrides target dependent heuristics used by default if has non zero value.
-
sched-pressure-algorithm
-
Choose between the two available implementations of -fsched-pressure. Algorithm 1 is the original implementation and is the more likely to prevent instructions from being reordered. Algorithm 2 was designed to be a compromise between the relatively conservative approach taken by algorithm 1 and the rather aggressive approach taken by the default scheduler. It relies more heavily on having a regular register file and accurate register pressure classes. See haifa-sched.c in the GCC sources for more details.
The default choice depends on the target.
-
max-slsr-cand-scan
-
Set the maximum number of existing candidates that will be considered when seeking a basis for a new straight-line strength reduction candidate.
Hardware Models and Configurations
Each target machine types can have its own special options, starting with
-m, to choose among various hardware models or configurations---for example, 68010 vs 68020, floating coprocessor or none. A single installed version of the compiler can compile for any model or configuration, according to the options specified.
Some configurations of the compiler also support additional special options, usually for compatibility with other compilers on the same platform.
AArch64 Options
These options are defined for AArch64 implementations:
-
-mbig-endian
-
Generate big-endian code. This is the default when GCC is configured for an aarch64_be-*-* target.
-
-mgeneral-regs-only
-
Generate code which uses only the general registers.
-
-mlittle-endian
-
Generate little-endian code. This is the default when GCC is configured for an aarch64-*-* but not an aarch64_be-*-* target.
-
-mcmodel=tiny
-
Generate code for the tiny code model. The program and its statically defined symbols must be within 1GB of each other. Pointers are 64 bits. Programs can be statically or dynamically linked. This model is not fully implemented and mostly treated as small.
-
-mcmodel=small
-
Generate code for the small code model. The program and its statically defined symbols must be within 4GB of each other. Pointers are 64 bits. Programs can be statically or dynamically linked. This is the default code model.
-
-mcmodel=large
-
Generate code for the large code model. This makes no assumptions about addresses and sizes of sections. Pointers are 64 bits. Programs can be statically linked only.
-
-mstrict-align
-
Do not assume that unaligned memory references will be handled by the system.
-
-momit-leaf-frame-pointer
-
-
-mno-omit-leaf-frame-pointer
-
Omit or keep the frame pointer in leaf functions. The former behaviour is the default.
-
-mtls-dialect=desc
-
Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables. This is the default.
-
-mtls-dialect=traditional
-
Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables.
-
-march=name
-
Specify the name of the target architecture, optionally suffixed by one or more feature modifiers. This option has the form -march=arch{+[no]feature}*, where the only value for arch is armv8-a. The possible values for feature are documented in the sub-section below.
Where conflicting feature modifiers are specified, the right-most feature is used.
GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead of the -mcpu= option.
-
-mcpu=name
-
Specify the name of the target processor, optionally suffixed by one or more feature modifiers. This option has the form -mcpu=cpu{+[no]feature}*, where the possible values for cpu are generic, large. The possible values for feature are documented in the sub-section below.
Where conflicting feature modifiers are specified, the right-most feature is used.
GCC uses this name to determine what kind of instructions it can emit when generating assembly code.
-
-mtune=name
-
Specify the name of the processor to tune the performance for. The code will be tuned as if the target processor were of the type specified in this option, but still using instructions compatible with the target processor specified by a -mcpu= option. This option cannot be suffixed by feature modifiers.
-march and -mcpu feature modifiers
Feature modifiers used with -march and -mcpu can be one the following:
-
crypto
-
Enable Crypto extension. This implies Advanced SIMD is enabled.
-
fp
-
Enable floating-point instructions.
-
simd
-
Enable Advanced SIMD instructions. This implies floating-point instructions are enabled. This is the default for all current possible values for options -march and -mcpu=.
Adapteva Epiphany Options
These -m options are defined for Adapteva Epiphany:
-
-mhalf-reg-file
-
Don't allocate any register in the range "r32"..."r63". That allows code to run on hardware variants that lack these registers.
-
-mprefer-short-insn-regs
-
Preferrentially allocate registers that allow short instruction generation. This can result in increased instruction count, so this may either reduce or increase overall code size.
-
-mbranch-cost=num
-
Set the cost of branches to roughly num "simple" instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases.
-
-mcmove
-
Enable the generation of conditional moves.
-
-mnops=num
-
Emit num NOPs before every other generated instruction.
-
-mno-soft-cmpsf
-
For single-precision floating-point comparisons, emit an "fsub" instruction and test the flags. This is faster than a software comparison, but can get incorrect results in the presence of NaNs, or when two different small numbers are compared such that their difference is calculated as zero. The default is -msoft-cmpsf, which uses slower, but IEEE-compliant, software comparisons.
-
-mstack-offset=num
-
Set the offset between the top of the stack and the stack pointer. E.g., a value of 8 means that the eight bytes in the range "sp+0...sp+7" can be used by leaf functions without stack allocation. Values other than 8 or 16 are untested and unlikely to work. Note also that this option changes the ABI; compiling a program with a different stack offset than the libraries have been compiled with generally does not work. This option can be useful if you want to evaluate if a different stack offset would give you better code, but to actually use a different stack offset to build working programs, it is recommended to configure the toolchain with the appropriate --with-stack-offset=num option.
-
-mno-round-nearest
-
Make the scheduler assume that the rounding mode has been set to truncating. The default is -mround-nearest.
-
-mlong-calls
-
If not otherwise specified by an attribute, assume all calls might be beyond the offset range of the "b" / "bl" instructions, and therefore load the function address into a register before performing a (otherwise direct) call. This is the default.
-
-mshort-calls
-
If not otherwise specified by an attribute, assume all direct calls are in the range of the "b" / "bl" instructions, so use these instructions for direct calls. The default is -mlong-calls.
-
-msmall16
-
Assume addresses can be loaded as 16-bit unsigned values. This does not apply to function addresses for which -mlong-calls semantics are in effect.
-
-mfp-mode=mode
-
Set the prevailing mode of the floating-point unit. This determines the floating-point mode that is provided and expected at function call and return time. Making this mode match the mode you predominantly need at function start can make your programs smaller and faster by avoiding unnecessary mode switches.
mode can be set to one the following values:
-
caller
-
Any mode at function entry is valid, and retained or restored when the function returns, and when it calls other functions. This mode is useful for compiling libraries or other compilation units you might want to incorporate into different programs with different prevailing FPU modes, and the convenience of being able to use a single object file outweighs the size and speed overhead for any extra mode switching that might be needed, compared with what would be needed with a more specific choice of prevailing FPU mode.
-
truncate
-
This is the mode used for floating-point calculations with truncating (i.e. round towards zero) rounding mode. That includes conversion from floating point to integer.
-
round-nearest
-
This is the mode used for floating-point calculations with round-to-nearest-or-even rounding mode.
-
int
-
This is the mode used to perform integer calculations in the FPU, e.g. integer multiply, or integer multiply-and-accumulate.
The default is
-mfp-mode=caller
-
-mnosplit-lohi
-
-
-mno-postinc
-
-
-mno-postmodify
-
Code generation tweaks that disable, respectively, splitting of 32-bit loads, generation of post-increment addresses, and generation of post-modify addresses. The defaults are msplit-lohi, -mpost-inc, and -mpost-modify.
-
-mnovect-double
-
Change the preferred SIMD mode to SImode. The default is -mvect-double, which uses DImode as preferred SIMD mode.
-
-max-vect-align=num
-
The maximum alignment for SIMD vector mode types. num may be 4 or 8. The default is 8. Note that this is an ABI change, even though many library function interfaces are unaffected if they don't use SIMD vector modes in places that affect size and/or alignment of relevant types.
-
-msplit-vecmove-early
-
Split vector moves into single word moves before reload. In theory this can give better register allocation, but so far the reverse seems to be generally the case.
-
-m1reg-reg
-
Specify a register to hold the constant -1, which makes loading small negative constants and certain bitmasks faster. Allowable values for reg are r43 and r63, which specify use of that register as a fixed register, and none, which means that no register is used for this purpose. The default is -m1reg-none.
ARM Options
These -m options are defined for Advanced RISC Machines (ARM) architectures:
-
-mabi=name
-
Generate code for the specified ABI. Permissible values are: apcs-gnu, atpcs, aapcs, aapcs-linux and iwmmxt.
-
-mapcs-frame
-
Generate a stack frame that is compliant with the ARM Procedure Call Standard for all functions, even if this is not strictly necessary for correct execution of the code. Specifying -fomit-frame-pointer with this option causes the stack frames not to be generated for leaf functions. The default is -mno-apcs-frame.
-
-mapcs
-
This is a synonym for -mapcs-frame.
-
-mthumb-interwork
-
Generate code that supports calling between the ARM and Thumb instruction sets. Without this option, on pre-v5 architectures, the two instruction sets cannot be reliably used inside one program. The default is -mno-thumb-interwork, since slightly larger code is generated when -mthumb-interwork is specified. In AAPCS configurations this option is meaningless.
-
-mno-sched-prolog
-
Prevent the reordering of instructions in the function prologue, or the merging of those instruction with the instructions in the function's body. This means that all functions start with a recognizable set of instructions (or in fact one of a choice from a small set of different function prologues), and this information can be used to locate the start of functions inside an executable piece of code. The default is -msched-prolog.
-
-mfloat-abi=name
-
Specifies which floating-point ABI to use. Permissible values are: soft, softfp and hard.
Specifying soft causes GCC to generate output containing library calls for floating-point operations. softfp allows the generation of code using hardware floating-point instructions, but still uses the soft-float calling conventions. hard allows generation of floating-point instructions and uses FPU-specific calling conventions.
The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.
-
-mlittle-endian
-
Generate code for a processor running in little-endian mode. This is the default for all standard configurations.
-
-mbig-endian
-
Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor.
-
-mwords-little-endian
-
This option only applies when generating code for big-endian processors. Generate code for a little-endian word order but a big-endian byte order. That is, a byte order of the form 32107654. Note: this option should only be used if you require compatibility with code for big-endian ARM processors generated by versions of the compiler prior to 2.8. This option is now deprecated.
-
-mcpu=name
-
This specifies the name of the target ARM processor. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. Permissible names are: arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, arm700i, arm710, arm710c, arm7100, arm720, arm7500, arm7500fe, arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm740t, strongarm, strongarm110, strongarm1100, strongarm1110, arm8, arm810, arm9, arm9e, arm920, arm920t, arm922t, arm946e-s, arm966e-s, arm968e-s, arm926ej-s, arm940t, arm9tdmi, arm10tdmi, arm1020t, arm1026ej-s, arm10e, arm1020e, arm1022e, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1156t2-s, arm1156t2f-s, arm1176jz-s, arm1176jzf-s, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a15, cortex-r4, cortex-r4f, cortex-r5, cortex-m4, cortex-m3, cortex-m1, cortex-m0, cortex-m0plus, marvell-pj4, xscale, iwmmxt, iwmmxt2, ep9312, fa526, fa626, fa606te, fa626te, fmp626, fa726te.
-mcpu=generic-arch is also permissible, and is equivalent to -march=arch -mtune=generic-arch. See -mtune for more information.
-mcpu=native causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-
-mtune=name
-
This option is very similar to the -mcpu= option, except that instead of specifying the actual target processor type, and hence restricting which instructions can be used, it specifies that GCC should tune the performance of the code as if the target were of the type specified in this option, but still choosing the instructions it generates based on the CPU specified by a -mcpu= option. For some ARM implementations better performance can be obtained by using this option.
-mtune=generic-arch specifies that GCC should tune the performance for a blend of processors within architecture arch. The aim is to generate code that run well on the current most popular processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go.
-mtune=native causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-
-march=name
-
This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead of the -mcpu= option. Permissible names are: armv2, armv2a, armv3, armv3m, armv4, armv4t, armv5, armv5t, armv5e, armv5te, armv6, armv6j, armv6t2, armv6z, armv6zk, armv6-m, armv7, armv7-a, armv7-r, armv7-m, armv8-a, iwmmxt, iwmmxt2, ep9312.
-march=native causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect.
-
-mfpu=name
-
This specifies what floating-point hardware (or hardware emulation) is available on the target. Permissible names are: vfp, vfpv3, vfpv3-fp16, vfpv3-d16, vfpv3-d16-fp16, vfpv3xd, vfpv3xd-fp16, neon, neon-fp16, vfpv4, vfpv4-d16, fpv4-sp-d16, neon-vfpv4, fp-armv8, neon-fp-armv8, and crypto-neon-fp-armv8.
If -msoft-float is specified this specifies the format of floating-point values.
If the selected floating-point hardware includes the NEON extension (e.g. -mfpu=neon), note that floating-point operations are not generated by GCC's auto-vectorization pass unless -funsafe-math-optimizations is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of NEON instructions may lead to a loss of precision.
-
-mfp16-format=name
-
Specify the format of the "__fp16" half-precision floating-point type. Permissible names are none, ieee, and alternative; the default is none, in which case the "__fp16" type is not defined.
-
-mstructure-size-boundary=n
-
The sizes of all structures and unions are rounded up to a multiple of the number of bits set by this option. Permissible values are 8, 32 and 64. The default value varies for different toolchains. For the COFF targeted toolchain the default value is 8. A value of 64 is only allowed if the underlying ABI supports it.
Specifying a larger number can produce faster, more efficient code, but can also increase the size of the program. Different values are potentially incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions.
-
-mabort-on-noreturn
-
Generate a call to the function "abort" at the end of a "noreturn" function. It is executed if the function tries to return.
-
-mlong-calls
-
-
-mno-long-calls
-
Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 64-megabyte addressing range of the offset-based version of subroutine call instruction.
Even if this switch is enabled, not all function calls are turned into long calls. The heuristic is that static functions, functions that have the short-call attribute, functions that are inside the scope of a #pragma no_long_calls directive, and functions whose definitions have already been compiled within the current compilation unit are not turned into long calls. The exceptions to this rule are that weak function definitions, functions with the long-call attribute or the section attribute, and functions that are within the scope of a #pragma long_calls directive are always turned into long calls.
This feature is not enabled by default. Specifying -mno-long-calls restores the default behavior, as does placing the function calls within the scope of a #pragma long_calls_off directive. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers.
-
-msingle-pic-base
-
Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins.
-
-mpic-register=reg
-
Specify the register to be used for PIC addressing. For standard PIC base case, the default will be any suitable register determined by compiler. For single PIC base case, the default is R9 if target is EABI based or stack-checking is enabled, otherwise the default is R10.
-
-mpoke-function-name
-
Write the name of each function into the text section, directly preceding the function prologue. The generated code is similar to this:
t0
.ascii "arm_poke_function_name", 0
.align
t1
.word 0xff000000 + (t1 - t0)
arm_poke_function_name
mov ip, sp
stmfd sp!, {fp, ip, lr, pc}
sub fp, ip, #4
When performing a stack backtrace, code can inspect the value of "pc" stored at "fp + 0". If the trace function then looks at location "pc - 12" and the top 8 bits are set, then we know that there is a function name embedded immediately preceding this location and has length "((pc[-3]) & 0xff000000)".
-
-mthumb
-
-
-marm
-
Select between generating code that executes in ARM and Thumb states. The default for most configurations is to generate code that executes in ARM state, but the default can be changed by configuring GCC with the --with-mode=state configure option.
-
-mtpcs-frame
-
Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all non-leaf functions. (A leaf function is one that does not call any other functions.) The default is -mno-tpcs-frame.
-
-mtpcs-leaf-frame
-
Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all leaf functions. (A leaf function is one that does not call any other functions.) The default is -mno-apcs-leaf-frame.
-
-mcallee-super-interworking
-
Gives all externally visible functions in the file being compiled an ARM instruction set header which switches to Thumb mode before executing the rest of the function. This allows these functions to be called from non-interworking code. This option is not valid in AAPCS configurations because interworking is enabled by default.
-
-mcaller-super-interworking
-
Allows calls via function pointers (including virtual functions) to execute correctly regardless of whether the target code has been compiled for interworking or not. There is a small overhead in the cost of executing a function pointer if this option is enabled. This option is not valid in AAPCS configurations because interworking is enabled by default.
-
-mtp=name
-
Specify the access model for the thread local storage pointer. The valid models are soft, which generates calls to "__aeabi_read_tp", cp15, which fetches the thread pointer from "cp15" directly (supported in the arm6k architecture), and auto, which uses the best available method for the selected processor. The default setting is auto.
-
-mtls-dialect=dialect
-
Specify the dialect to use for accessing thread local storage. Two dialects are supported---gnu and gnu2. The gnu dialect selects the original GNU scheme for supporting local and global dynamic TLS models. The gnu2 dialect selects the GNU descriptor scheme, which provides better performance for shared libraries. The GNU descriptor scheme is compatible with the original scheme, but does require new assembler, linker and library support. Initial and local exec TLS models are unaffected by this option and always use the original scheme.
-
-mword-relocations
-
Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). This is enabled by default on targets (uClinux, SymbianOS) where the runtime loader imposes this restriction, and when -fpic or -fPIC is specified.
-
-mfix-cortex-m3-ldrd
-
Some Cortex-M3 cores can cause data corruption when "ldrd" instructions with overlapping destination and base registers are used. This option avoids generating these instructions. This option is enabled by default when -mcpu=cortex-m3 is specified.
-
-munaligned-access
-
-
-mno-unaligned-access
-
Enables (or disables) reading and writing of 16- and 32- bit values from addresses that are not 16- or 32- bit aligned. By default unaligned access is disabled for all pre-ARMv6 and all ARMv6-M architectures, and enabled for all other architectures. If unaligned access is not enabled then words in packed data structures will be accessed a byte at a time.
The ARM attribute "Tag_CPU_unaligned_access" will be set in the generated object file to either true or false, depending upon the setting of this option. If unaligned access is enabled then the preprocessor symbol "__ARM_FEATURE_UNALIGNED" will also be defined.
AVR Options
These options are defined for AVR implementations:
-
-mmcu=mcu
-
Specify Atmel AVR instruction set architectures (ISA) or MCU type.
The default for this option is@tie{}"avr2".
GCC supports the following AVR devices and ISAs:
-
"avr2"
-
"Classic" devices with up to 8@tie{}KiB of program memory. mcu@tie{}= "attiny22", "attiny26", "at90c8534", "at90s2313", "at90s2323", "at90s2333", "at90s2343", "at90s4414", "at90s4433", "at90s4434", "at90s8515", "at90s8535".
-
"avr25"
-
"Classic" devices with up to 8@tie{}KiB of program memory and with the "MOVW" instruction. mcu@tie{}= "ata5272", "ata6289", "attiny13", "attiny13a", "attiny2313", "attiny2313a", "attiny24", "attiny24a", "attiny25", "attiny261", "attiny261a", "attiny43u", "attiny4313", "attiny44", "attiny44a", "attiny45", "attiny461", "attiny461a", "attiny48", "attiny84", "attiny84a", "attiny85", "attiny861", "attiny861a", "attiny87", "attiny88", "at86rf401".
-
"avr3"
-
"Classic" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. mcu@tie{}= "at43usb355", "at76c711".
-
"avr31"
-
"Classic" devices with 128@tie{}KiB of program memory. mcu@tie{}= "atmega103", "at43usb320".
-
"avr35"
-
"Classic" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory and with the "MOVW" instruction. mcu@tie{}= "ata5505", "atmega16u2", "atmega32u2", "atmega8u2", "attiny1634", "attiny167", "at90usb162", "at90usb82".
-
"avr4"
-
"Enhanced" devices with up to 8@tie{}KiB of program memory. mcu@tie{}= "ata6285", "ata6286", "atmega48", "atmega48a", "atmega48p", "atmega48pa", "atmega8", "atmega8a", "atmega8hva", "atmega8515", "atmega8535", "atmega88", "atmega88a", "atmega88p", "atmega88pa", "at90pwm1", "at90pwm2", "at90pwm2b", "at90pwm3", "at90pwm3b", "at90pwm81".
-
"avr5"
-
"Enhanced" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. mcu@tie{}= "ata5790", "ata5790n", "ata5795", "atmega16", "atmega16a", "atmega16hva", "atmega16hva2", "atmega16hvb", "atmega16hvbrevb", "atmega16m1", "atmega16u4", "atmega161", "atmega162", "atmega163", "atmega164a", "atmega164p", "atmega164pa", "atmega165", "atmega165a", "atmega165p", "atmega165pa", "atmega168", "atmega168a", "atmega168p", "atmega168pa", "atmega169", "atmega169a", "atmega169p", "atmega169pa", "atmega26hvg", "atmega32", "atmega32a", "atmega32c1", "atmega32hvb", "atmega32hvbrevb", "atmega32m1", "atmega32u4", "atmega32u6", "atmega323", "atmega324a", "atmega324p", "atmega324pa", "atmega325", "atmega325a", "atmega325p", "atmega3250", "atmega3250a", "atmega3250p", "atmega3250pa", "atmega328", "atmega328p", "atmega329", "atmega329a", "atmega329p", "atmega329pa", "atmega3290", "atmega3290a", "atmega3290p", "atmega3290pa", "atmega406", "atmega48hvf", "atmega64", "atmega64a", "atmega64c1", "atmega64hve", "atmega64m1", "atmega64rfa2", "atmega64rfr2", "atmega640", "atmega644", "atmega644a", "atmega644p", "atmega644pa", "atmega645", "atmega645a", "atmega645p", "atmega6450", "atmega6450a", "atmega6450p", "atmega649", "atmega649a", "atmega649p", "atmega6490", "atmega6490a", "atmega6490p", "at90can32", "at90can64", "at90pwm161", "at90pwm216", "at90pwm316", "at90scr100", "at90usb646", "at90usb647", "at94k", "m3000".
-
"avr51"
-
"Enhanced" devices with 128@tie{}KiB of program memory. mcu@tie{}= "atmega128", "atmega128a", "atmega128rfa1", "atmega1280", "atmega1281", "atmega1284", "atmega1284p", "at90can128", "at90usb1286", "at90usb1287".
-
"avr6"
-
"Enhanced" devices with 3-byte PC, i.e. with more than 128@tie{}KiB of program memory. mcu@tie{}= "atmega2560", "atmega2561".
-
"avrxmega2"
-
"XMEGA" devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory. mcu@tie{}= "atmxt112sl", "atmxt224", "atmxt224e", "atmxt336s", "atxmega16a4", "atxmega16a4u", "atxmega16c4", "atxmega16d4", "atxmega16x1", "atxmega32a4", "atxmega32a4u", "atxmega32c4", "atxmega32d4", "atxmega32e5", "atxmega32x1".
-
"avrxmega4"
-
"XMEGA" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory. mcu@tie{}= "atxmega64a3", "atxmega64a3u", "atxmega64a4u", "atxmega64b1", "atxmega64b3", "atxmega64c3", "atxmega64d3", "atxmega64d4".
-
"avrxmega5"
-
"XMEGA" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of RAM. mcu@tie{}= "atxmega64a1", "atxmega64a1u".
-
"avrxmega6"
-
"XMEGA" devices with more than 128@tie{}KiB of program memory. mcu@tie{}= "atmxt540s", "atmxt540sreva", "atxmega128a3", "atxmega128a3u", "atxmega128b1", "atxmega128b3", "atxmega128c3", "atxmega128d3", "atxmega128d4", "atxmega192a3", "atxmega192a3u", "atxmega192c3", "atxmega192d3", "atxmega256a3", "atxmega256a3b", "atxmega256a3bu", "atxmega256a3u", "atxmega256c3", "atxmega256d3", "atxmega384c3", "atxmega384d3".
-
"avrxmega7"
-
"XMEGA" devices with more than 128@tie{}KiB of program memory and more than 64@tie{}KiB of RAM. mcu@tie{}= "atxmega128a1", "atxmega128a1u", "atxmega128a4u".
-
"avr1"
-
This ISA is implemented by the minimal AVR core and supported for assembler only. mcu@tie{}= "attiny11", "attiny12", "attiny15", "attiny28", "at90s1200".
-
-maccumulate-args
-
Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments once in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards.
Popping the arguments after the function call can be expensive on AVR so that accumulating the stack space might lead to smaller executables because arguments need not to be removed from the stack after such a function call.
This option can lead to reduced code size for functions that perform several calls to functions that get their arguments on the stack like calls to printf-like functions.
-
-mbranch-cost=cost
-
Set the branch costs for conditional branch instructions to cost. Reasonable values for cost are small, non-negative integers. The default branch cost is 0.
-
-mcall-prologues
-
Functions prologues/epilogues are expanded as calls to appropriate subroutines. Code size is smaller.
-
-mint8
-
Assume "int" to be 8-bit integer. This affects the sizes of all types: a "char" is 1 byte, an "int" is 1 byte, a "long" is 2 bytes, and "long long" is 4 bytes. Please note that this option does not conform to the C standards, but it results in smaller code size.
-
-mno-interrupts
-
Generated code is not compatible with hardware interrupts. Code size is smaller.
-
-mrelax
-
Try to replace "CALL" resp. "JMP" instruction by the shorter "RCALL" resp. "RJMP" instruction if applicable. Setting "-mrelax" just adds the "--relax" option to the linker command line when the linker is called.
Jump relaxing is performed by the linker because jump offsets are not known before code is located. Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable may differ from instructions in the assembler code.
Relaxing must be turned on if linker stubs are needed, see the section on "EIND" and linker stubs below.
-
-msp8
-
Treat the stack pointer register as an 8-bit register, i.e. assume the high byte of the stack pointer is zero. In general, you don't need to set this option by hand.
This option is used internally by the compiler to select and build multilibs for architectures "avr2" and "avr25". These architectures mix devices with and without "SPH". For any setting other than "-mmcu=avr2" or "-mmcu=avr25" the compiler driver will add or remove this option from the compiler proper's command line, because the compiler then knows if the device or architecture has an 8-bit stack pointer and thus no "SPH" register or not.
-
-mstrict-X
-
Use address register "X" in a way proposed by the hardware. This means that "X" is only used in indirect, post-increment or pre-decrement addressing.
Without this option, the "X" register may be used in the same way as "Y" or "Z" which then is emulated by additional instructions. For example, loading a value with "X+const" addressing with a small non-negative "const < 64" to a register Rn is performed as
adiw r26, const ; X += const
ld <Rn>, X ; <Rn> = *X
sbiw r26, const ; X -= const
-
-mtiny-stack
-
Only change the lower 8@tie{}bits of the stack pointer.
-
-Waddr-space-convert
-
Warn about conversions between address spaces in the case where the resulting address space is not contained in the incoming address space.
"EIND" and Devices with more than 128 Ki Bytes of Flash
Pointers in the implementation are 16@tie{}bits wide. The address of a function or label is represented as word address so that indirect jumps and calls can target any code address in the range of 64@tie{}Ki words.
In order to facilitate indirect jump on devices with more than 128@tie{}Ki bytes of program memory space, there is a special function register called "EIND" that serves as most significant part of the target address when "EICALL" or "EIJMP" instructions are used.
Indirect jumps and calls on these devices are handled as follows by the compiler and are subject to some limitations:
-
•
-
The compiler never sets "EIND".
-
•
-
The compiler uses "EIND" implicitely in "EICALL"/"EIJMP" instructions or might read "EIND" directly in order to emulate an indirect call/jump by means of a "RET" instruction.
-
•
-
The compiler assumes that "EIND" never changes during the startup code or during the application. In particular, "EIND" is not saved/restored in function or interrupt service routine prologue/epilogue.
-
•
-
For indirect calls to functions and computed goto, the linker generates stubs. Stubs are jump pads sometimes also called trampolines. Thus, the indirect call/jump jumps to such a stub. The stub contains a direct jump to the desired address.
-
•
-
Linker relaxation must be turned on so that the linker will generate the stubs correctly an all situaltion. See the compiler option "-mrelax" and the linler option "--relax". There are corner cases where the linker is supposed to generate stubs but aborts without relaxation and without a helpful error message.
-
•
-
The default linker script is arranged for code with "EIND = 0". If code is supposed to work for a setup with "EIND != 0", a custom linker script has to be used in order to place the sections whose name start with ".trampolines" into the segment where "EIND" points to.
-
•
-
The startup code from libgcc never sets "EIND". Notice that startup code is a blend of code from libgcc and AVR-LibC. For the impact of AVR-LibC on "EIND", see the AVR-LibC user manual ("http://nongnu.org/avr-libc/user-manual/").
-
•
-
It is legitimate for user-specific startup code to set up "EIND" early, for example by means of initialization code located in section ".init3". Such code runs prior to general startup code that initializes RAM and calls constructors, but after the bit of startup code from AVR-LibC that sets "EIND" to the segment where the vector table is located.
#include <avr/io.h>
static void
__attribute__((section(".init3"),naked,used,no_instrument_function))
init3_set_eind (void)
{
__asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t"
"out %i0,r24" :: "n" (&EIND) : "r24","memory");
}
The "__trampolines_start" symbol is defined in the linker script.
-
•
-
Stubs are generated automatically by the linker if the following two conditions are met:
-
-<The address of a label is taken by means of the "gs" modifier>
-
(short for generate stubs) like so:
LDI r24, lo8(gs(<func>))
LDI r25, hi8(gs(<func>))
-
-<The final location of that label is in a code segment>
-
outside the segment where the stubs are located.
-
•
-
The compiler emits such "gs" modifiers for code labels in the following situations:
-
-<Taking address of a function or code label.>
-
-
-<Computed goto.>
-
-
-<If prologue-save function is used, see -mcall-prologues>
-
command-line option.
-
-<Switch/case dispatch tables. If you do not want such dispatch>
-
tables you can specify the -fno-jump-tables command-line option.
-
-<C and C++ constructors/destructors called during startup/shutdown.>
-
-
-<If the tools hit a "gs()" modifier explained above.>
-
-
•
-
Jumping to non-symbolic addresses like so is not supported:
int main (void)
{
/* Call function at word address 0x2 */
return ((int(*)(void)) 0x2)();
}
Instead, a stub has to be set up, i.e. the function has to be called through a symbol ("func_4" in the example):
int main (void)
{
extern int func_4 (void);
/* Call function at byte address 0x4 */
return func_4();
}
and the application be linked with "-Wl,--defsym,func_4=0x4". Alternatively, "func_4" can be defined in the linker script.
Handling of the "RAMPD", "RAMPX", "RAMPY" and "RAMPZ" Special Function Registers
Some AVR devices support memories larger than the 64@tie{}KiB range that can be accessed with 16-bit pointers. To access memory locations outside this 64@tie{}KiB range, the contentent of a "RAMP" register is used as high part of the address: The "X", "Y", "Z" address register is concatenated with the "RAMPX", "RAMPY", "RAMPZ" special function register, respectively, to get a wide address. Similarly, "RAMPD" is used together with direct addressing.
-
•
-
The startup code initializes the "RAMP" special function registers with zero.
-
•
-
If a AVR Named Address Spaces,named address space other than generic or "__flash" is used, then "RAMPZ" is set as needed before the operation.
-
•
-
If the device supports RAM larger than 64@tie{KiB} and the compiler needs to change "RAMPZ" to accomplish an operation, "RAMPZ" is reset to zero after the operation.
-
•
-
If the device comes with a specific "RAMP" register, the ISR prologue/epilogue saves/restores that SFR and initializes it with zero in case the ISR code might (implicitly) use it.
-
•
-
RAM larger than 64@tie{KiB} is not supported by GCC for AVR targets. If you use inline assembler to read from locations outside the 16-bit address range and change one of the "RAMP" registers, you must reset it to zero after the access.
AVR Built-in Macros
GCC defines several built-in macros so that the user code can test for the presence or absence of features. Almost any of the following built-in macros are deduced from device capabilities and thus triggered by the "-mmcu=" command-line option.
For even more AVR-specific built-in macros see AVR Named Address Spaces and AVR Built-in Functions.
-
"__AVR_ARCH__"
-
Build-in macro that resolves to a decimal number that identifies the architecture and depends on the "-mmcu= mcu" option. Possible values are:
2, 25, 3, 31, 35, 4, 5, 51, 6, 102, 104, 105, 106, 107
for mcu="avr2", "avr25", "avr3", "avr31", "avr35", "avr4", "avr5", "avr51", "avr6", "avrxmega2", "avrxmega4", "avrxmega5", "avrxmega6", "avrxmega7", respectively. If mcu specifies a device, this built-in macro is set accordingly. For example, with "-mmcu=atmega8" the macro will be defined to 4.
-
"__AVR_Device__"
-
Setting "-mmcu=device" defines this built-in macro which reflects the device's name. For example, "-mmcu=atmega8" defines the built-in macro "__AVR_ATmega8__", "-mmcu=attiny261a" defines "__AVR_ATtiny261A__", etc.
The built-in macros' names follow the scheme "__AVR_ Device__" where Device is the device name as from the AVR user manual. The difference between Device in the built-in macro and device in "-mmcu= device" is that the latter is always lowercase.
If device is not a device but only a core architecture like "avr51", this macro will not be defined.
-
"__AVR_XMEGA__"
-
The device / architecture belongs to the XMEGA family of devices.
-
"__AVR_HAVE_ELPM__"
-
The device has the the "ELPM" instruction.
-
"__AVR_HAVE_ELPMX__"
-
The device has the "ELPM Rn,Z" and "ELPM R n,Z+" instructions.
-
"__AVR_HAVE_MOVW__"
-
The device has the "MOVW" instruction to perform 16-bit register-register moves.
-
"__AVR_HAVE_LPMX__"
-
The device has the "LPM Rn,Z" and "LPM R n,Z+" instructions.
-
"__AVR_HAVE_MUL__"
-
The device has a hardware multiplier.
-
"__AVR_HAVE_JMP_CALL__"
-
The device has the "JMP" and "CALL" instructions. This is the case for devices with at least 16@tie{}KiB of program memory.
-
"__AVR_HAVE_EIJMP_EICALL__"
-
-
"__AVR_3_BYTE_PC__"
-
The device has the "EIJMP" and "EICALL" instructions. This is the case for devices with more than 128@tie{}KiB of program memory. This also means that the program counter (PC) is 3@tie{}bytes wide.
-
"__AVR_2_BYTE_PC__"
-
The program counter (PC) is 2@tie{}bytes wide. This is the case for devices with up to 128@tie{}KiB of program memory.
-
"__AVR_HAVE_8BIT_SP__"
-
-
"__AVR_HAVE_16BIT_SP__"
-
The stack pointer (SP) register is treated as 8-bit respectively 16-bit register by the compiler. The definition of these macros is affected by "-mtiny-stack".
-
"__AVR_HAVE_SPH__"
-
-
"__AVR_SP8__"
-
The device has the SPH (high part of stack pointer) special function register or has an 8-bit stack pointer, respectively. The definition of these macros is affected by "-mmcu=" and in the cases of "-mmcu=avr2" and "-mmcu=avr25" also by "-msp8".
-
"__AVR_HAVE_RAMPD__"
-
-
"__AVR_HAVE_RAMPX__"
-
-
"__AVR_HAVE_RAMPY__"
-
-
"__AVR_HAVE_RAMPZ__"
-
The device has the "RAMPD", "RAMPX", "RAMPY", "RAMPZ" special function register, respectively.
-
"__NO_INTERRUPTS__"
-
This macro reflects the "-mno-interrupts" command line option.
-
"__AVR_ERRATA_SKIP__"
-
-
"__AVR_ERRATA_SKIP_JMP_CALL__"
-
Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit instructions because of a hardware erratum. Skip instructions are "SBRS", "SBRC", "SBIS", "SBIC" and "CPSE". The second macro is only defined if "__AVR_HAVE_JMP_CALL__" is also set.
-
"__AVR_SFR_OFFSET__=offset"
-
Instructions that can address I/O special function registers directly like "IN", "OUT", "SBI", etc. may use a different address as if addressed by an instruction to access RAM like "LD" or "STS". This offset depends on the device architecture and has to be subtracted from the RAM address in order to get the respective I/O@tie{}address.
-
"__WITH_AVRLIBC__"
-
The compiler is configured to be used together with AVR-Libc. See the "--with-avrlibc" configure option.
Blackfin Options
-
-mcpu=cpu[-sirevision]
-
Specifies the name of the target Blackfin processor. Currently, cpu can be one of bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf536, bf537, bf538, bf539, bf542, bf544, bf547, bf548, bf549, bf542m, bf544m, bf547m, bf548m, bf549m, bf561, bf592.
The optional sirevision specifies the silicon revision of the target Blackfin processor. Any workarounds available for the targeted silicon revision are enabled. If sirevision is none, no workarounds are enabled. If sirevision is any, all workarounds for the targeted processor are enabled. The "__SILICON_REVISION__" macro is defined to two hexadecimal digits representing the major and minor numbers in the silicon revision. If sirevision is none, the "__SILICON_REVISION__" is not defined. If sirevision is any, the "__SILICON_REVISION__" is defined to be 0xffff. If this optional sirevision is not used, GCC assumes the latest known silicon revision of the targeted Blackfin processor.
GCC defines a preprocessor macro for the specified cpu. For the bfin-elf toolchain, this option causes the hardware BSP provided by libgloss to be linked in if -msim is not given.
Without this option, bf532 is used as the processor by default.
Note that support for bf561 is incomplete. For bf561, only the preprocessor macro is defined.
-
-msim
-
Specifies that the program will be run on the simulator. This causes the simulator BSP provided by libgloss to be linked in. This option has effect only for bfin-elf toolchain. Certain other options, such as -mid-shared-library and -mfdpic, imply -msim.
-
-momit-leaf-frame-pointer
-
Don't keep the frame pointer in a register for leaf functions. This avoids the instructions to save, set up and restore frame pointers and makes an extra register available in leaf functions. The option -fomit-frame-pointer removes the frame pointer for all functions, which might make debugging harder.
-
-mspecld-anomaly
-
When enabled, the compiler ensures that the generated code does not contain speculative loads after jump instructions. If this option is used, "__WORKAROUND_SPECULATIVE_LOADS" is defined.
-
-mno-specld-anomaly
-
Don't generate extra code to prevent speculative loads from occurring.
-
-mcsync-anomaly
-
When enabled, the compiler ensures that the generated code does not contain CSYNC or SSYNC instructions too soon after conditional branches. If this option is used, "__WORKAROUND_SPECULATIVE_SYNCS" is defined.
-
-mno-csync-anomaly
-
Don't generate extra code to prevent CSYNC or SSYNC instructions from occurring too soon after a conditional branch.
-
-mlow-64k
-
When enabled, the compiler is free to take advantage of the knowledge that the entire program fits into the low 64k of memory.
-
-mno-low-64k
-
Assume that the program is arbitrarily large. This is the default.
-
-mstack-check-l1
-
Do stack checking using information placed into L1 scratchpad memory by the uClinux kernel.
-
-mid-shared-library
-
Generate code that supports shared libraries via the library ID method. This allows for execute in place and shared libraries in an environment without virtual memory management. This option implies -fPIC. With a bfin-elf target, this option implies -msim.
-
-mno-id-shared-library
-
Generate code that doesn't assume ID-based shared libraries are being used. This is the default.
-
-mleaf-id-shared-library
-
Generate code that supports shared libraries via the library ID method, but assumes that this library or executable won't link against any other ID shared libraries. That allows the compiler to use faster code for jumps and calls.
-
-mno-leaf-id-shared-library
-
Do not assume that the code being compiled won't link against any ID shared libraries. Slower code is generated for jump and call insns.
-
-mshared-library-id=n
-
Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0 generates more compact code; specifying other values forces the allocation of that number to the current library but is no more space- or time-efficient than omitting this option.
-
-msep-data
-
Generate code that allows the data segment to be located in a different area of memory from the text segment. This allows for execute in place in an environment without virtual memory management by eliminating relocations against the text section.
-
-mno-sep-data
-
Generate code that assumes that the data segment follows the text segment. This is the default.
-
-mlong-calls
-
-
-mno-long-calls
-
Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function lies outside of the 24-bit addressing range of the offset-based version of subroutine call instruction.
This feature is not enabled by default. Specifying -mno-long-calls restores the default behavior. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers.
-
-mfast-fp
-
Link with the fast floating-point library. This library relaxes some of the IEEE floating-point standard's rules for checking inputs against Not-a-Number (NAN), in the interest of performance.
-
-minline-plt
-
Enable inlining of PLT entries in function calls to functions that are not known to bind locally. It has no effect without -mfdpic.
-
-mmulticore
-
Build a standalone application for multicore Blackfin processors. This option causes proper start files and link scripts supporting multicore to be used, and defines the macro "__BFIN_MULTICORE". It can only be used with -mcpu=bf561[-sirevision].
This option can be used with -mcorea or -mcoreb, which selects the one-application-per-core programming model. Without -mcorea or -mcoreb, the single-application/dual-core programming model is used. In this model, the main function of Core B should be named as "coreb_main".
If this option is not used, the single-core application programming model is used.
-
-mcorea
-
Build a standalone application for Core A of BF561 when using the one-application-per-core programming model. Proper start files and link scripts are used to support Core A, and the macro "__BFIN_COREA" is defined. This option can only be used in conjunction with -mmulticore.
-
-mcoreb
-
Build a standalone application for Core B of BF561 when using the one-application-per-core programming model. Proper start files and link scripts are used to support Core B, and the macro "__BFIN_COREB" is defined. When this option is used, "coreb_main" should be used instead of "main". This option can only be used in conjunction with -mmulticore.
-
-msdram
-
Build a standalone application for SDRAM. Proper start files and link scripts are used to put the application into SDRAM, and the macro "__BFIN_SDRAM" is defined. The loader should initialize SDRAM before loading the application.
-
-micplb
-
Assume that ICPLBs are enabled at run time. This has an effect on certain anomaly workarounds. For Linux targets, the default is to assume ICPLBs are enabled; for standalone applications the default is off.
C6X Options
-
-march=name
-
This specifies the name of the target architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. Permissible names are: c62x, c64x, c64x+, c67x, c67x+, c674x.
-
-mbig-endian
-
Generate code for a big-endian target.
-
-mlittle-endian
-
Generate code for a little-endian target. This is the default.
-
-msim
-
Choose startup files and linker script suitable for the simulator.
-
-msdata=default
-
Put small global and static data in the .neardata section, which is pointed to by register "B14". Put small uninitialized global and static data in the .bss section, which is adjacent to the .neardata section. Put small read-only data into the .rodata section. The corresponding sections used for large pieces of data are .fardata, .far and .const.
-
-msdata=all
-
Put all data, not just small objects, into the sections reserved for small data, and use addressing relative to the "B14" register to access them.
-
-msdata=none
-
Make no use of the sections reserved for small data, and use absolute addresses to access all data. Put all initialized global and static data in the .fardata section, and all uninitialized data in the .far section. Put all constant data into the .const section.
CRIS Options
These options are defined specifically for the CRIS ports.
-
-march=architecture-type
-
-
-mcpu=architecture-type
-
Generate code for the specified architecture. The choices for architecture-type are v3, v8 and v10 for respectively ETRAX 4, ETRAX 100, and ETRAX 100 LX. Default is v0 except for cris-axis-linux-gnu, where the default is v10.
-
-mtune=architecture-type
-
Tune to architecture-type everything applicable about the generated code, except for the ABI and the set of available instructions. The choices for architecture-type are the same as for -march=architecture-type.
-
-mmax-stack-frame=n
-
Warn when the stack frame of a function exceeds n bytes.
-
-metrax4
-
-
-metrax100
-
The options -metrax4 and -metrax100 are synonyms for -march=v3 and -march=v8 respectively.
-
-mmul-bug-workaround
-
-
-mno-mul-bug-workaround
-
Work around a bug in the "muls" and "mulu" instructions for CPU models where it applies. This option is active by default.
-
-mpdebug
-
Enable CRIS-specific verbose debug-related information in the assembly code. This option also has the effect of turning off the #NO_APP formatted-code indicator to the assembler at the beginning of the assembly file.
-
-mcc-init
-
Do not use condition-code results from previous instruction; always emit compare and test instructions before use of condition codes.
-
-mno-side-effects
-
Do not emit instructions with side effects in addressing modes other than post-increment.
-
-mstack-align
-
-
-mno-stack-align
-
-
-mdata-align
-
-
-mno-data-align
-
-
-mconst-align
-
-
-mno-const-align
-
These options (no- options) arrange (eliminate arrangements) for the stack frame, individual data and constants to be aligned for the maximum single data access size for the chosen CPU model. The default is to arrange for 32-bit alignment. ABI details such as structure layout are not affected by these options.
-
-m32-bit
-
-
-m16-bit
-
-
-m8-bit
-
Similar to the stack- data- and const-align options above, these options arrange for stack frame, writable data and constants to all be 32-bit, 16-bit or 8-bit aligned. The default is 32-bit alignment.
-
-mno-prologue-epilogue
-
-
-mprologue-epilogue
-
With -mno-prologue-epilogue, the normal function prologue and epilogue which set up the stack frame are omitted and no return instructions or return sequences are generated in the code. Use this option only together with visual inspection of the compiled code: no warnings or errors are generated when call-saved registers must be saved, or storage for local variables needs to be allocated.
-
-mno-gotplt
-
-
-mgotplt
-
With -fpic and -fPIC, don't generate (do generate) instruction sequences that load addresses for functions from the PLT part of the GOT rather than (traditional on other architectures) calls to the PLT. The default is -mgotplt.
-
-melf
-
Legacy no-op option only recognized with the cris-axis-elf and cris-axis-linux-gnu targets.
-
-mlinux
-
Legacy no-op option only recognized with the cris-axis-linux-gnu target.
-
-sim
-
This option, recognized for the cris-axis-elf, arranges to link with input-output functions from a simulator library. Code, initialized data and zero-initialized data are allocated consecutively.
-
-sim2
-
Like -sim, but pass linker options to locate initialized data at 0x40000000 and zero-initialized data at 0x80000000.
CR16 Options
These options are defined specifically for the CR16 ports.
-
-mmac
-
Enable the use of multiply-accumulate instructions. Disabled by default.
-
-mcr16cplus
-
-
-mcr16c
-
Generate code for CR16C or CR16C+ architecture. CR16C+ architecture is default.
-
-msim
-
Links the library libsim.a which is in compatible with simulator. Applicable to ELF compiler only.
-
-mint32
-
Choose integer type as 32-bit wide.
-
-mbit-ops
-
Generates "sbit"/"cbit" instructions for bit manipulations.
-
-mdata-model=model
-
Choose a data model. The choices for model are near, far or medium. medium is default. However, far is not valid with -mcr16c, as the CR16C architecture does not support the far data model.
Darwin Options
These options are defined for all architectures running the Darwin operating system.
FSF GCC on Darwin does not create "fat" object files; it creates an object file for the single architecture that GCC was built to target. Apple's GCC on Darwin does create "fat" files if multiple -arch options are used; it does so by running the compiler or linker multiple times and joining the results together with lipo.
The subtype of the file created (like ppc7400 or ppc970 or i686) is determined by the flags that specify the ISA that GCC is targeting, like -mcpu or -march. The -force_cpusubtype_ALL option can be used to override this.
The Darwin tools vary in their behavior when presented with an ISA mismatch. The assembler, as, only permits instructions to be used that are valid for the subtype of the file it is generating, so you cannot put 64-bit instructions in a ppc750 object file. The linker for shared libraries, /usr/bin/libtool, fails and prints an error if asked to create a shared library with a less restrictive subtype than its input files (for instance, trying to put a ppc970 object file in a ppc7400 library). The linker for executables, ld, quietly gives the executable the most restrictive subtype of any of its input files.
-
-Fdir
-
Add the framework directory dir to the head of the list of directories to be searched for header files. These directories are interleaved with those specified by -I options and are scanned in a left-to-right order.
A framework directory is a directory with frameworks in it. A framework is a directory with a Headers and/or PrivateHeaders directory contained directly in it that ends in .framework. The name of a framework is the name of this directory excluding the .framework. Headers associated with the framework are found in one of those two directories, with Headers being searched first. A subframework is a framework directory that is in a framework's Frameworks directory. Includes of subframework headers can only appear in a header of a framework that contains the subframework, or in a sibling subframework header. Two subframeworks are siblings if they occur in the same framework. A subframework should not have the same name as a framework; a warning is issued if this is violated. Currently a subframework cannot have subframeworks; in the future, the mechanism may be extended to support this. The standard frameworks can be found in /System/Library/Frameworks and /Library/Frameworks. An example include looks like "#include <Framework/header.h>", where Framework denotes the name of the framework and header.h is found in the PrivateHeaders or Headers directory.
-
-iframeworkdir
-
Like -F except the directory is a treated as a system directory. The main difference between this -iframework and -F is that with -iframework the compiler does not warn about constructs contained within header files found via dir. This option is valid only for the C family of languages.
-
-gused
-
Emit debugging information for symbols that are used. For stabs debugging format, this enables -feliminate-unused-debug-symbols. This is by default ON.
-
-gfull
-
Emit debugging information for all symbols and types.
-
-mmacosx-version-min=version
-
The earliest version of MacOS X that this executable will run on is version. Typical values of version include 10.1, 10.2, and 10.3.9.
If the compiler was built to use the system's headers by default, then the default for this option is the system version on which the compiler is running, otherwise the default is to make choices that are compatible with as many systems and code bases as possible.
-
-mkernel
-
Enable kernel development mode. The -mkernel option sets -static, -fno-common, -fno-cxa-atexit, -fno-exceptions, -fno-non-call-exceptions, -fapple-kext, -fno-weak and -fno-rtti where applicable. This mode also sets -mno-altivec, -msoft-float, -fno-builtin and -mlong-branch for PowerPC targets.
-
-mone-byte-bool
-
Override the defaults for bool so that sizeof(bool)==1. By default sizeof(bool) is 4 when compiling for Darwin/PowerPC and 1 when compiling for Darwin/x86, so this option has no effect on x86.
Warning: The -mone-byte-bool switch causes GCC to generate code that is not binary compatible with code generated without that switch. Using this switch may require recompiling all other modules in a program, including system libraries. Use this switch to conform to a non-default data model.
-
-mfix-and-continue
-
-
-ffix-and-continue
-
-
-findirect-data
-
Generate code suitable for fast turnaround development, such as to allow GDB to dynamically load ".o" files into already-running programs. -findirect-data and -ffix-and-continue are provided for backwards compatibility.
-
-all_load
-
Loads all members of static archive libraries. See man ld(1) for more information.
-
-arch_errors_fatal
-
Cause the errors having to do with files that have the wrong architecture to be fatal.
-
-bind_at_load
-
Causes the output file to be marked such that the dynamic linker will bind all undefined references when the file is loaded or launched.
-
-bundle
-
Produce a Mach-o bundle format file. See man ld(1) for more information.
-
-bundle_loader executable
-
This option specifies the executable that will load the build output file being linked. See man ld(1) for more information.
-
-dynamiclib
-
When passed this option, GCC produces a dynamic library instead of an executable when linking, using the Darwin libtool command.
-
-force_cpusubtype_ALL
-
This causes GCC's output file to have the ALL subtype, instead of one controlled by the -mcpu or -march option.
-
-allowable_client client_name
-
-
-client_name
-
-
-compatibility_version
-
-
-current_version
-
-
-dead_strip
-
-
-dependency-file
-
-
-dylib_file
-
-
-dylinker_install_name
-
-
-dynamic
-
-
-exported_symbols_list
-
-
-filelist
-
-
-flat_namespace
-
-
-force_flat_namespace
-
-
-headerpad_max_install_names
-
-
-image_base
-
-
-init
-
-
-install_name
-
-
-keep_private_externs
-
-
-multi_module
-
-
-multiply_defined
-
-
-multiply_defined_unused
-
-
-noall_load
-
-
-no_dead_strip_inits_and_terms
-
-
-nofixprebinding
-
-
-nomultidefs
-
-
-noprebind
-
-
-noseglinkedit
-
-
-pagezero_size
-
-
-prebind
-
-
-prebind_all_twolevel_modules
-
-
-private_bundle
-
-
-read_only_relocs
-
-
-sectalign
-
-
-sectobjectsymbols
-
-
-whyload
-
-
-seg1addr
-
-
-sectcreate
-
-
-sectobjectsymbols
-
-
-sectorder
-
-
-segaddr
-
-
-segs_read_only_addr
-
-
-segs_read_write_addr
-
-
-seg_addr_table
-
-
-seg_addr_table_filename
-
-
-seglinkedit
-
-
-segprot
-
-
-segs_read_only_addr
-
-
-segs_read_write_addr
-
-
-single_module
-
-
-static
-
-
-sub_library
-
-
-sub_umbrella
-
-
-twolevel_namespace
-
-
-umbrella
-
-
-undefined
-
-
-unexported_symbols_list
-
-
-weak_reference_mismatches
-
-
-whatsloaded
-
These options are passed to the Darwin linker. The Darwin linker man page describes them in detail.
DEC Alpha Options
These -m options are defined for the DEC Alpha implementations:
-
-mno-soft-float
-
-
-msoft-float
-
Use (do not use) the hardware floating-point instructions for floating-point operations. When -msoft-float is specified, functions in libgcc.a are used to perform floating-point operations. Unless they are replaced by routines that emulate the floating-point operations, or compiled in such a way as to call such emulations routines, these routines issue floating-point operations. If you are compiling for an Alpha without floating-point operations, you must ensure that the library is built so as not to call them.
Note that Alpha implementations without floating-point operations are required to have floating-point registers.
-
-mfp-reg
-
-
-mno-fp-regs
-
Generate code that uses (does not use) the floating-point register set. -mno-fp-regs implies -msoft-float. If the floating-point register set is not used, floating-point operands are passed in integer registers as if they were integers and floating-point results are passed in $0 instead of $f0. This is a non-standard calling sequence, so any function with a floating-point argument or return value called by code compiled with -mno-fp-regs must also be compiled with that option.
A typical use of this option is building a kernel that does not use, and hence need not save and restore, any floating-point registers.
-
-mieee
-
The Alpha architecture implements floating-point hardware optimized for maximum performance. It is mostly compliant with the IEEE floating-point standard. However, for full compliance, software assistance is required. This option generates code fully IEEE-compliant code except that the inexact-flag is not maintained (see below). If this option is turned on, the preprocessor macro "_IEEE_FP" is defined during compilation. The resulting code is less efficient but is able to correctly support denormalized numbers and exceptional IEEE values such as not-a-number and plus/minus infinity. Other Alpha compilers call this option -ieee_with_no_inexact.
-
-mieee-with-inexact
-
This is like -mieee except the generated code also maintains the IEEE inexact-flag. Turning on this option causes the generated code to implement fully-compliant IEEE math. In addition to "_IEEE_FP", "_IEEE_FP_EXACT" is defined as a preprocessor macro. On some Alpha implementations the resulting code may execute significantly slower than the code generated by default. Since there is very little code that depends on the inexact-flag, you should normally not specify this option. Other Alpha compilers call this option -ieee_with_inexact.
-
-mfp-trap-mode=trap-mode
-
This option controls what floating-point related traps are enabled. Other Alpha compilers call this option -fptm trap-mode. The trap mode can be set to one of four values:
-
n
-
This is the default (normal) setting. The only traps that are enabled are the ones that cannot be disabled in software (e.g., division by zero trap).
-
u
-
In addition to the traps enabled by n, underflow traps are enabled as well.
-
su
-
Like u, but the instructions are marked to be safe for software completion (see Alpha architecture manual for details).
-
sui
-
Like su, but inexact traps are enabled as well.
-
-mfp-rounding-mode=rounding-mode
-
Selects the IEEE rounding mode. Other Alpha compilers call this option -fprm rounding-mode. The rounding-mode can be one of:
-
n
-
Normal IEEE rounding mode. Floating-point numbers are rounded towards the nearest machine number or towards the even machine number in case of a tie.
-
m
-
Round towards minus infinity.
-
c
-
Chopped rounding mode. Floating-point numbers are rounded towards zero.
-
d
-
Dynamic rounding mode. A field in the floating-point control register ( fpcr, see Alpha architecture reference manual) controls the rounding mode in effect. The C library initializes this register for rounding towards plus infinity. Thus, unless your program modifies the fpcr, d corresponds to round towards plus infinity.
-
-mtrap-precision=trap-precision
-
In the Alpha architecture, floating-point traps are imprecise. This means without software assistance it is impossible to recover from a floating trap and program execution normally needs to be terminated. GCC can generate code that can assist operating system trap handlers in determining the exact location that caused a floating-point trap. Depending on the requirements of an application, different levels of precisions can be selected:
-
p
-
Program precision. This option is the default and means a trap handler can only identify which program caused a floating-point exception.
-
f
-
Function precision. The trap handler can determine the function that caused a floating-point exception.
-
i
-
Instruction precision. The trap handler can determine the exact instruction that caused a floating-point exception.
Other Alpha compilers provide the equivalent options called
-scope_safe and
-resumption_safe.
-
-mieee-conformant
-
This option marks the generated code as IEEE conformant. You must not use this option unless you also specify -mtrap-precision=i and either -mfp-trap-mode=su or -mfp-trap-mode=sui. Its only effect is to emit the line .eflag 48 in the function prologue of the generated assembly file.
-
-mbuild-constants
-
Normally GCC examines a 32- or 64-bit integer constant to see if it can construct it from smaller constants in two or three instructions. If it cannot, it outputs the constant as a literal and generates code to load it from the data segment at run time.
Use this option to require GCC to construct all integer constants using code, even if it takes more instructions (the maximum is six).
You typically use this option to build a shared library dynamic loader. Itself a shared library, it must relocate itself in memory before it can find the variables and constants in its own data segment.
-
-mbwx
-
-
-mno-bwx
-
-
-mcix
-
-
-mno-cix
-
-
-mfix
-
-
-mno-fix
-
-
-mmax
-
-
-mno-max
-
Indicate whether GCC should generate code to use the optional BWX, CIX, FIX and MAX instruction sets. The default is to use the instruction sets supported by the CPU type specified via -mcpu= option or that of the CPU on which GCC was built if none is specified.
-
-mfloat-vax
-
-
-mfloat-ieee
-
Generate code that uses (does not use) VAX F and G floating-point arithmetic instead of IEEE single and double precision.
-
-mexplicit-relocs
-
-
-mno-explicit-relocs
-
Older Alpha assemblers provided no way to generate symbol relocations except via assembler macros. Use of these macros does not allow optimal instruction scheduling. GNU binutils as of version 2.12 supports a new syntax that allows the compiler to explicitly mark which relocations should apply to which instructions. This option is mostly useful for debugging, as GCC detects the capabilities of the assembler when it is built and sets the default accordingly.
-
-msmall-data
-
-
-mlarge-data
-
When -mexplicit-relocs is in effect, static data is accessed via gp-relative relocations. When -msmall-data is used, objects 8 bytes long or smaller are placed in a small data area (the ".sdata" and ".sbss" sections) and are accessed via 16-bit relocations off of the $gp register. This limits the size of the small data area to 64KB, but allows the variables to be directly accessed via a single instruction.
The default is -mlarge-data. With this option the data area is limited to just below 2GB. Programs that require more than 2GB of data must use "malloc" or "mmap" to allocate the data in the heap instead of in the program's data segment.
When generating code for shared libraries, -fpic implies -msmall-data and -fPIC implies -mlarge-data.
-
-msmall-text
-
-
-mlarge-text
-
When -msmall-text is used, the compiler assumes that the code of the entire program (or shared library) fits in 4MB, and is thus reachable with a branch instruction. When -msmall-data is used, the compiler can assume that all local symbols share the same $gp value, and thus reduce the number of instructions required for a function call from 4 to 1.
The default is -mlarge-text.
-
-mcpu=cpu_type
-
Set the instruction set and instruction scheduling parameters for machine type cpu_type. You can specify either the EV style name or the corresponding chip number. GCC supports scheduling parameters for the EV4, EV5 and EV6 family of processors and chooses the default values for the instruction set from the processor you specify. If you do not specify a processor type, GCC defaults to the processor on which the compiler was built.
Supported values for cpu_type are
-
ev4
-
-
ev45
-
-
21064
-
Schedules as an EV4 and has no instruction set extensions.
-
ev5
-
-
21164
-
Schedules as an EV5 and has no instruction set extensions.
-
ev56
-
-
21164a
-
Schedules as an EV5 and supports the BWX extension.
-
pca56
-
-
21164pc
-
-
21164PC
-
Schedules as an EV5 and supports the BWX and MAX extensions.
-
ev6
-
-
21264
-
Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
-
ev67
-
-
21264a
-
Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
Native toolchains also support the value
native, which selects the best architecture option for the host processor.
-mcpu=native has no effect if GCC does not recognize the processor.
-
-mtune=cpu_type
-
Set only the instruction scheduling parameters for machine type cpu_type. The instruction set is not changed.
Native toolchains also support the value native, which selects the best architecture option for the host processor. -mtune=native has no effect if GCC does not recognize the processor.
-
-mmemory-latency=time
-
Sets the latency the scheduler should assume for typical memory references as seen by the application. This number is highly dependent on the memory access patterns used by the application and the size of the external cache on the machine.
Valid options for time are
-
number
-
A decimal number representing clock cycles.
-
L1
-
-
L2
-
-
L3
-
-
main
-
The compiler contains estimates of the number of clock cycles for "typical" EV4 & EV5 hardware for the Level 1, 2 & 3 caches (also called Dcache, Scache, and Bcache), as well as to main memory. Note that L3 is only valid for EV5.
FR30 Options
These options are defined specifically for the FR30 port.
-
-msmall-model
-
Use the small address space model. This can produce smaller code, but it does assume that all symbolic values and addresses fit into a 20-bit range.
-
-mno-lsim
-
Assume that runtime support has been provided and so there is no need to include the simulator library ( libsim.a) on the linker command line.
FRV Options
-
-mgpr-32
-
Only use the first 32 general-purpose registers.
-
-mgpr-64
-
Use all 64 general-purpose registers.
-
-mfpr-32
-
Use only the first 32 floating-point registers.
-
-mfpr-64
-
Use all 64 floating-point registers.
-
-mhard-float
-
Use hardware instructions for floating-point operations.
-
-msoft-float
-
Use library routines for floating-point operations.
-
-malloc-cc
-
Dynamically allocate condition code registers.
-
-mfixed-cc
-
Do not try to dynamically allocate condition code registers, only use "icc0" and "fcc0".
-
-mdword
-
Change ABI to use double word insns.
-
-mno-dword
-
Do not use double word instructions.
-
-mdouble
-
Use floating-point double instructions.
-
-mno-double
-
Do not use floating-point double instructions.
-
-mmedia
-
Use media instructions.
-
-mno-media
-
Do not use media instructions.
-
-mmuladd
-
Use multiply and add/subtract instructions.
-
-mno-muladd
-
Do not use multiply and add/subtract instructions.
-
-mfdpic
-
Select the FDPIC ABI, which uses function descriptors to represent pointers to functions. Without any PIC/PIE-related options, it implies -fPIE. With -fpic or -fpie, it assumes GOT entries and small data are within a 12-bit range from the GOT base address; with -fPIC or -fPIE, GOT offsets are computed with 32 bits. With a bfin-elf target, this option implies -msim.
-
-minline-plt
-
Enable inlining of PLT entries in function calls to functions that are not known to bind locally. It has no effect without -mfdpic. It's enabled by default if optimizing for speed and compiling for shared libraries (i.e., -fPIC or -fpic), or when an optimization option such as -O3 or above is present in the command line.
-
-mTLS
-
Assume a large TLS segment when generating thread-local code.
-
-mtls
-
Do not assume a large TLS segment when generating thread-local code.
-
-mgprel-ro
-
Enable the use of "GPREL" relocations in the FDPIC ABI for data that is known to be in read-only sections. It's enabled by default, except for -fpic or -fpie: even though it may help make the global offset table smaller, it trades 1 instruction for 4. With -fPIC or -fPIE, it trades 3 instructions for 4, one of which may be shared by multiple symbols, and it avoids the need for a GOT entry for the referenced symbol, so it's more likely to be a win. If it is not, -mno-gprel-ro can be used to disable it.
-
-multilib-library-pic
-
Link with the (library, not FD) pic libraries. It's implied by -mlibrary-pic, as well as by -fPIC and -fpic without -mfdpic. You should never have to use it explicitly.
-
-mlinked-fp
-
Follow the EABI requirement of always creating a frame pointer whenever a stack frame is allocated. This option is enabled by default and can be disabled with -mno-linked-fp.
-
-mlong-calls
-
Use indirect addressing to call functions outside the current compilation unit. This allows the functions to be placed anywhere within the 32-bit address space.
-
-malign-labels
-
Try to align labels to an 8-byte boundary by inserting NOPs into the previous packet. This option only has an effect when VLIW packing is enabled. It doesn't create new packets; it merely adds NOPs to existing ones.
-
-mlibrary-pic
-
Generate position-independent EABI code.
-
-macc-4
-
Use only the first four media accumulator registers.
-
-macc-8
-
Use all eight media accumulator registers.
-
-mpack
-
Pack VLIW instructions.
-
-mno-pack
-
Do not pack VLIW instructions.
-
-mno-eflags
-
Do not mark ABI switches in e_flags.
-
-mcond-move
-
Enable the use of conditional-move instructions (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mno-cond-move
-
Disable the use of conditional-move instructions.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mscc
-
Enable the use of conditional set instructions (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mno-scc
-
Disable the use of conditional set instructions.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mcond-exec
-
Enable the use of conditional execution (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mno-cond-exec
-
Disable the use of conditional execution.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mvliw-branch
-
Run a pass to pack branches into VLIW instructions (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mno-vliw-branch
-
Do not run a pass to pack branches into VLIW instructions.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mmulti-cond-exec
-
Enable optimization of "&&" and "||" in conditional execution (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mno-multi-cond-exec
-
Disable optimization of "&&" and "||" in conditional execution.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mnested-cond-exec
-
Enable nested conditional execution optimizations (default).
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-mno-nested-cond-exec
-
Disable nested conditional execution optimizations.
This switch is mainly for debugging the compiler and will likely be removed in a future version.
-
-moptimize-membar
-
This switch removes redundant "membar" instructions from the compiler-generated code. It is enabled by default.
-
-mno-optimize-membar
-
This switch disables the automatic removal of redundant "membar" instructions from the generated code.
-
-mtomcat-stats
-
Cause gas to print out tomcat statistics.
-
-mcpu=cpu
-
Select the processor type for which to generate code. Possible values are frv, fr550, tomcat, fr500, fr450, fr405, fr400, fr300 and simple.
GNU/Linux Options
These -m options are defined for GNU/Linux targets:
-
-mglibc
-
Use the GNU C library. This is the default except on *-*-linux-*uclibc* and *-*-linux-*android* targets.
-
-muclibc
-
Use uClibc C library. This is the default on *-*-linux-*uclibc* targets.
-
-mbionic
-
Use Bionic C library. This is the default on *-*-linux-*android* targets.
-
-mandroid
-
Compile code compatible with Android platform. This is the default on *-*-linux-*android* targets.
When compiling, this option enables -mbionic, -fPIC, -fno-exceptions and -fno-rtti by default. When linking, this option makes the GCC driver pass Android-specific options to the linker. Finally, this option causes the preprocessor macro "__ANDROID__" to be defined.
-
-tno-android-cc
-
Disable compilation effects of -mandroid, i.e., do not enable -mbionic, -fPIC, -fno-exceptions and -fno-rtti by default.
-
-tno-android-ld
-
Disable linking effects of -mandroid, i.e., pass standard Linux linking options to the linker.
H8/300 Options
These -m options are defined for the H8/300 implementations:
-
-mrelax
-
Shorten some address references at link time, when possible; uses the linker option -relax.
-
-mh
-
Generate code for the H8/300H.
-
-ms
-
Generate code for the H8S.
-
-mn
-
Generate code for the H8S and H8/300H in the normal mode. This switch must be used either with -mh or -ms.
-
-ms2600
-
Generate code for the H8S/2600. This switch must be used with -ms.
-
-mexr
-
Extended registers are stored on stack before execution of function with monitor attribute. Default option is -mexr. This option is valid only for H8S targets.
-
-mno-exr
-
Extended registers are not stored on stack before execution of function with monitor attribute. Default option is -mno-exr. This option is valid only for H8S targets.
-
-mint32
-
Make "int" data 32 bits by default.
-
-malign-300
-
On the H8/300H and H8S, use the same alignment rules as for the H8/300. The default for the H8/300H and H8S is to align longs and floats on 4-byte boundaries. -malign-300 causes them to be aligned on 2-byte boundaries. This option has no effect on the H8/300.
HPPA Options
These -m options are defined for the HPPA family of computers:
-
-march=architecture-type
-
Generate code for the specified architecture. The choices for architecture-type are 1.0 for PA 1.0, 1.1 for PA 1.1, and 2.0 for PA 2.0 processors. Refer to /usr/lib/sched.models on an HP-UX system to determine the proper architecture option for your machine. Code compiled for lower numbered architectures runs on higher numbered architectures, but not the other way around.
-
-mpa-risc-1-0
-
-
-mpa-risc-1-1
-
-
-mpa-risc-2-0
-
Synonyms for -march=1.0, -march=1.1, and -march=2.0 respectively.
-
-mbig-switch
-
Generate code suitable for big switch tables. Use this option only if the assembler/linker complain about out-of-range branches within a switch table.
-
-mjump-in-delay
-
Fill delay slots of function calls with unconditional jump instructions by modifying the return pointer for the function call to be the target of the conditional jump.
-
-mdisable-fpregs
-
Prevent floating-point registers from being used in any manner. This is necessary for compiling kernels that perform lazy context switching of floating-point registers. If you use this option and attempt to perform floating-point operations, the compiler aborts.
-
-mdisable-indexing
-
Prevent the compiler from using indexing address modes. This avoids some rather obscure problems when compiling MIG generated code under MACH.
-
-mno-space-regs
-
Generate code that assumes the target has no space registers. This allows GCC to generate faster indirect calls and use unscaled index address modes.
Such code is suitable for level 0 PA systems and kernels.
-
-mfast-indirect-calls
-
Generate code that assumes calls never cross space boundaries. This allows GCC to emit code that performs faster indirect calls.
This option does not work in the presence of shared libraries or nested functions.
-
-mfixed-range=register-range
-
Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.
-
-mlong-load-store
-
Generate 3-instruction load and store sequences as sometimes required by the HP-UX 10 linker. This is equivalent to the +k option to the HP compilers.
-
-mportable-runtime
-
Use the portable calling conventions proposed by HP for ELF systems.
-
-mgas
-
Enable the use of assembler directives only GAS understands.
-
-mschedule=cpu-type
-
Schedule code according to the constraints for the machine type cpu-type. The choices for cpu-type are 700 7100, 7100LC, 7200, 7300 and 8000. Refer to /usr/lib/sched.models on an HP-UX system to determine the proper scheduling option for your machine. The default scheduling is 8000.
-
-mlinker-opt
-
Enable the optimization pass in the HP-UX linker. Note this makes symbolic debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9 linkers in which they give bogus error messages when linking some programs.
-
-msoft-float
-
Generate output containing library calls for floating point. Warning: the requisite libraries are not available for all HPPA targets. Normally the facilities of the machine's usual C compiler are used, but this cannot be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation.
-msoft-float changes the calling convention in the output file; therefore, it is only useful if you compile all of a program with this option. In particular, you need to compile libgcc.a, the library that comes with GCC, with -msoft-float in order for this to work.
-
-msio
-
Generate the predefine, "_SIO", for server IO. The default is -mwsio. This generates the predefines, "__hp9000s700", "__hp9000s700__" and "_WSIO", for workstation IO. These options are available under HP-UX and HI-UX.
-
-mgnu-ld
-
Use options specific to GNU ld. This passes -shared to ld when building a shared library. It is the default when GCC is configured, explicitly or implicitly, with the GNU linker. This option does not affect which ld is called; it only changes what parameters are passed to that ld. The ld that is called is determined by the --with-ld configure option, GCC's program search path, and finally by the user's PATH. The linker used by GCC can be printed using which `gcc -print-prog-name=ld`. This option is only available on the 64-bit HP-UX GCC, i.e. configured with hppa*64*-*-hpux*.
-
-mhp-ld
-
Use options specific to HP ld. This passes -b to ld when building a shared library and passes +Accept TypeMismatch to ld on all links. It is the default when GCC is configured, explicitly or implicitly, with the HP linker. This option does not affect which ld is called; it only changes what parameters are passed to that ld. The ld that is called is determined by the --with-ld configure option, GCC's program search path, and finally by the user's PATH. The linker used by GCC can be printed using which `gcc -print-prog-name=ld`. This option is only available on the 64-bit HP-UX GCC, i.e. configured with hppa*64*-*-hpux*.
-
-mlong-calls
-
Generate code that uses long call sequences. This ensures that a call is always able to reach linker generated stubs. The default is to generate long calls only when the distance from the call site to the beginning of the function or translation unit, as the case may be, exceeds a predefined limit set by the branch type being used. The limits for normal calls are 7,600,000 and 240,000 bytes, respectively for the PA 2.0 and PA 1.X architectures. Sibcalls are always limited at 240,000 bytes.
Distances are measured from the beginning of functions when using the -ffunction-sections option, or when using the -mgas and -mno-portable-runtime options together under HP-UX with the SOM linker.
It is normally not desirable to use this option as it degrades performance. However, it may be useful in large applications, particularly when partial linking is used to build the application.
The types of long calls used depends on the capabilities of the assembler and linker, and the type of code being generated. The impact on systems that support long absolute calls, and long pic symbol-difference or pc-relative calls should be relatively small. However, an indirect call is used on 32-bit ELF systems in pic code and it is quite long.
-
-munix=unix-std
-
Generate compiler predefines and select a startfile for the specified UNIX standard. The choices for unix-std are 93, 95 and 98. 93 is supported on all HP-UX versions. 95 is available on HP-UX 10.10 and later. 98 is available on HP-UX 11.11 and later. The default values are 93 for HP-UX 10.00, 95 for HP-UX 10.10 though to 11.00, and 98 for HP-UX 11.11 and later.
-munix=93 provides the same predefines as GCC 3.3 and 3.4. -munix=95 provides additional predefines for "XOPEN_UNIX" and "_XOPEN_SOURCE_EXTENDED", and the startfile unix95.o. -munix=98 provides additional predefines for "_XOPEN_UNIX", "_XOPEN_SOURCE_EXTENDED", "_INCLUDE__STDC_A1_SOURCE" and "_INCLUDE_XOPEN_SOURCE_500", and the startfile unix98.o.
It is important to note that this option changes the interfaces for various library routines. It also affects the operational behavior of the C library. Thus, extreme care is needed in using this option.
Library code that is intended to operate with more than one UNIX standard must test, set and restore the variable __xpg4_extended_mask as appropriate. Most GNU software doesn't provide this capability.
-
-nolibdld
-
Suppress the generation of link options to search libdld.sl when the -static option is specified on HP-UX 10 and later.
-
-static
-
The HP-UX implementation of setlocale in libc has a dependency on libdld.sl. There isn't an archive version of libdld.sl. Thus, when the -static option is specified, special link options are needed to resolve this dependency.
On HP-UX 10 and later, the GCC driver adds the necessary options to link with libdld.sl when the -static option is specified. This causes the resulting binary to be dynamic. On the 64-bit port, the linkers generate dynamic binaries by default in any case. The -nolibdld option can be used to prevent the GCC driver from adding these link options.
-
-threads
-
Add support for multithreading with the dce thread library under HP-UX. This option sets flags for both the preprocessor and linker.
Intel 386 and AMD x86-64 Options
These -m options are defined for the i386 and x86-64 family of computers:
-
-march=cpu-type
-
Generate instructions for the machine type cpu-type. In contrast to -mtune=cpu-type, which merely tunes the generated code for the specified cpu-type, -march=cpu-type allows GCC to generate code that may not run at all on processors other than the one indicated. Specifying -march=cpu-type implies -mtune=cpu-type.
The choices for cpu-type are:
-
native
-
This selects the CPU to generate code for at compilation time by determining the processor type of the compiling machine. Using -march=native enables all instruction subsets supported by the local machine (hence the result might not run on different machines). Using -mtune=native produces code optimized for the local machine under the constraints of the selected instruction set.
-
i386
-
Original Intel i386 CPU.
-
i486
-
Intel i486 CPU. (No scheduling is implemented for this chip.)
-
i586
-
-
pentium
-
Intel Pentium CPU with no MMX support.
-
pentium-mmx
-
Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.
-
pentiumpro
-
Intel Pentium Pro CPU.
-
i686
-
When used with -march, the Pentium Pro instruction set is used, so the code runs on all i686 family chips. When used with -mtune, it has the same meaning as generic.
-
pentium2
-
Intel Pentium II CPU, based on Pentium Pro core with MMX instruction set support.
-
pentium3
-
-
pentium3m
-
Intel Pentium III CPU, based on Pentium Pro core with MMX and SSE instruction set support.
-
pentium-m
-
Intel Pentium M; low-power version of Intel Pentium III CPU with MMX, SSE and SSE2 instruction set support. Used by Centrino notebooks.
-
pentium4
-
-
pentium4m
-
Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction set support.
-
prescott
-
Improved version of Intel Pentium 4 CPU with MMX, SSE, SSE2 and SSE3 instruction set support.
-
nocona
-
Improved version of Intel Pentium 4 CPU with 64-bit extensions, MMX, SSE, SSE2 and SSE3 instruction set support.
-
core2
-
Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.
-
corei7
-
Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 instruction set support.
-
corei7-avx
-
Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES and PCLMUL instruction set support.
-
core-avx-i
-
Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support.
-
core-avx2
-
Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2 and F16C instruction set support.
-
atom
-
Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.
-
k6
-
AMD K6 CPU with MMX instruction set support.
-
k6-2
-
-
k6-3
-
Improved versions of AMD K6 CPU with MMX and 3DNow! instruction set support.
-
athlon
-
-
athlon-tbird
-
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow! and SSE prefetch instructions support.
-
athlon-4
-
-
athlon-xp
-
-
athlon-mp
-
Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow! and full SSE instruction set support.
-
k8
-
-
opteron
-
-
athlon64
-
-
athlon-fx
-
Processors based on the AMD K8 core with x86-64 instruction set support, including the AMD Opteron, Athlon 64, and Athlon 64 FX processors. (This supersets MMX, SSE, SSE2, 3DNow!, enhanced 3DNow! and 64-bit instruction set extensions.)
-
k8-sse3
-
-
opteron-sse3
-
-
athlon64-sse3
-
Improved versions of AMD K8 cores with SSE3 instruction set support.
-
amdfam10
-
-
barcelona
-
CPUs based on AMD Family 10h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit instruction set extensions.)
-
bdver1
-
CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
-
bdver2
-
AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
-
bdver3
-
AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.
-
btver1
-
CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit instruction set extensions.)
-
btver2
-
CPUs based on AMD Family 16h cores with x86-64 instruction set support. This includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.
-
winchip-c6
-
IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction set support.
-
winchip2
-
IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow! instruction set support.
-
c3
-
VIA C3 CPU with MMX and 3DNow! instruction set support. (No scheduling is implemented for this chip.)
-
c3-2
-
VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support. (No scheduling is implemented for this chip.)
-
geode
-
AMD Geode embedded processor with MMX and 3DNow! instruction set support.
-
-mtune=cpu-type
-
Tune to cpu-type everything applicable about the generated code, except for the ABI and the set of available instructions. While picking a specific cpu-type schedules things appropriately for that particular chip, the compiler does not generate any code that cannot run on the default machine type unless you use a -march=cpu-type option. For example, if GCC is configured for i686-pc-linux-gnu then -mtune=pentium4 generates code that is tuned for Pentium 4 but still runs on i686 machines.
The choices for cpu-type are the same as for -march. In addition, -mtune supports an extra choice for cpu-type:
-
generic
-
Produce code optimized for the most common IA32/AMD64/EM64T processors. If you know the CPU on which your code will run, then you should use the corresponding -mtune or -march option instead of -mtune=generic. But, if you do not know exactly what CPU users of your application will have, then you should use this option.
As new processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the processors that are most common at the time that version of GCC is released.
There is no -march=generic option because -march indicates the instruction set the compiler can use, and there is no generic instruction set applicable to all processors. In contrast, -mtune indicates the processor (or, in this case, collection of processors) for which the code is optimized.
-
-mcpu=cpu-type
-
A deprecated synonym for -mtune.
-
-mfpmath=unit
-
Generate floating-point arithmetic for selected unit unit. The choices for unit are:
-
387
-
Use the standard 387 floating-point coprocessor present on the majority of chips and emulated otherwise. Code compiled with this option runs almost everywhere. The temporary results are computed in 80-bit precision instead of the precision specified by the type, resulting in slightly different results compared to most of other chips. See -ffloat-store for more detailed description.
This is the default choice for i386 compiler.
-
sse
-
Use scalar floating-point instructions present in the SSE instruction set. This instruction set is supported by Pentium III and newer chips, and in the AMD line by Athlon-4, Athlon XP and Athlon MP chips. The earlier version of the SSE instruction set supports only single-precision arithmetic, thus the double and extended-precision arithmetic are still done using 387. A later version, present only in Pentium 4 and AMD x86-64 chips, supports double-precision arithmetic too.
For the i386 compiler, you must use -march=cpu-type, -msse or -msse2 switches to enable SSE extensions and make this option effective. For the x86-64 compiler, these extensions are enabled by default.
The resulting code should be considerably faster in the majority of cases and avoid the numerical instability problems of 387 code, but may break some existing code that expects temporaries to be 80 bits.
This is the default choice for the x86-64 compiler.
-
sse,387
-
-
sse+387
-
-
both
-
Attempt to utilize both instruction sets at once. This effectively doubles the amount of available registers, and on chips with separate execution units for 387 and SSE the execution resources too. Use this option with care, as it is still experimental, because the GCC register allocator does not model separate functional units well, resulting in unstable performance.
-
-masm=dialect
-
Output assembly instructions using selected dialect. Supported choices are intel or att (the default). Darwin does not support intel.
-
-mieee-fp
-
-
-mno-ieee-fp
-
Control whether or not the compiler uses IEEE floating-point comparisons. These correctly handle the case where the result of a comparison is unordered.
-
-msoft-float
-
Generate output containing library calls for floating point.
Warning: the requisite libraries are not part of GCC. Normally the facilities of the machine's usual C compiler are used, but this can't be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation.
On machines where a function returns floating-point results in the 80387 register stack, some floating-point opcodes may be emitted even if -msoft-float is used.
-
-mno-fp-ret-in-387
-
Do not use the FPU registers for return values of functions.
The usual calling convention has functions return values of types "float" and "double" in an FPU register, even if there is no FPU. The idea is that the operating system should emulate an FPU.
The option -mno-fp-ret-in-387 causes such values to be returned in ordinary CPU registers instead.
-
-mno-fancy-math-387
-
Some 387 emulators do not support the "sin", "cos" and "sqrt" instructions for the 387. Specify this option to avoid generating those instructions. This option is the default on FreeBSD, OpenBSD and NetBSD. This option is overridden when -march indicates that the target CPU always has an FPU and so the instruction does not need emulation. These instructions are not generated unless you also use the -funsafe-math-optimizations switch.
-
-malign-double
-
-
-mno-align-double
-
Control whether GCC aligns "double", "long double", and "long long" variables on a two-word boundary or a one-word boundary. Aligning "double" variables on a two-word boundary produces code that runs somewhat faster on a Pentium at the expense of more memory.
On x86-64, -malign-double is enabled by default.
Warning: if you use the -malign-double switch, structures containing the above types are aligned differently than the published application binary interface specifications for the 386 and are not binary compatible with structures in code compiled without that switch.
-
-m96bit-long-double
-
-
-m128bit-long-double
-
These switches control the size of "long double" type. The i386 application binary interface specifies the size to be 96 bits, so -m96bit-long-double is the default in 32-bit mode.
Modern architectures (Pentium and newer) prefer "long double" to be aligned to an 8- or 16-byte boundary. In arrays or structures conforming to the ABI, this is not possible. So specifying -m128bit-long-double aligns "long double" to a 16-byte boundary by padding the "long double" with an additional 32-bit zero.
In the x86-64 compiler, -m128bit-long-double is the default choice as its ABI specifies that "long double" is aligned on 16-byte boundary.
Notice that neither of these options enable any extra precision over the x87 standard of 80 bits for a "long double".
Warning: if you override the default value for your target ABI, this changes the size of structures and arrays containing "long double" variables, as well as modifying the function calling convention for functions taking "long double". Hence they are not binary-compatible with code compiled without that switch.
-
-mlong-double-64
-
-
-mlong-double-80
-
These switches control the size of "long double" type. A size of 64 bits makes the "long double" type equivalent to the "double" type. This is the default for Bionic C library.
Warning: if you override the default value for your target ABI, this changes the size of structures and arrays containing "long double" variables, as well as modifying the function calling convention for functions taking "long double". Hence they are not binary-compatible with code compiled without that switch.
-
-mlarge-data-threshold=threshold
-
When -mcmodel=medium is specified, data objects larger than threshold are placed in the large data section. This value must be the same across all objects linked into the binary, and defaults to 65535.
-
-mrtd
-
Use a different function-calling convention, in which functions that take a fixed number of arguments return with the "ret num" instruction, which pops their arguments while returning. This saves one instruction in the caller since there is no need to pop the arguments there.
You can specify that an individual function is called with this calling sequence with the function attribute stdcall. You can also override the -mrtd option by using the function attribute cdecl.
Warning: this calling convention is incompatible with the one normally used on Unix, so you cannot use it if you need to call libraries compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that take variable numbers of arguments (including "printf"); otherwise incorrect code is generated for calls to those functions.
In addition, seriously incorrect code results if you call a function with too many arguments. (Normally, extra arguments are harmlessly ignored.)
-
-mregparm=num
-
Control how many registers are used to pass integer arguments. By default, no registers are used to pass arguments, and at most 3 registers can be used. You can control this behavior for a specific function by using the function attribute regparm.
Warning: if you use this switch, and num is nonzero, then you must build all modules with the same value, including any libraries. This includes the system libraries and startup modules.
-
-msseregparm
-
Use SSE register passing conventions for float and double arguments and return values. You can control this behavior for a specific function by using the function attribute sseregparm.
Warning: if you use this switch then you must build all modules with the same value, including any libraries. This includes the system libraries and startup modules.
-
-mvect8-ret-in-mem
-
Return 8-byte vectors in memory instead of MMX registers. This is the default on Solaris@tie{}8 and 9 and VxWorks to match the ABI of the Sun Studio compilers until version 12. Later compiler versions (starting with Studio 12 Update@tie{}1) follow the ABI used by other x86 targets, which is the default on Solaris@tie{}10 and later. Only use this option if you need to remain compatible with existing code produced by those previous compiler versions or older versions of GCC.
-
-mpc32
-
-
-mpc64
-
-
-mpc80
-
Set 80387 floating-point precision to 32, 64 or 80 bits. When -mpc32 is specified, the significands of results of floating-point operations are rounded to 24 bits (single precision); -mpc64 rounds the significands of results of floating-point operations to 53 bits (double precision) and -mpc80 rounds the significands of results of floating-point operations to 64 bits (extended double precision), which is the default. When this option is used, floating-point operations in higher precisions are not available to the programmer without setting the FPU control word explicitly.
Setting the rounding of floating-point operations to less than the default 80 bits can speed some programs by 2% or more. Note that some mathematical libraries assume that extended-precision (80-bit) floating-point operations are enabled by default; routines in such libraries could suffer significant loss of accuracy, typically through so-called "catastrophic cancellation", when this option is used to set the precision to less than extended precision.
-
-mstackrealign
-
Realign the stack at entry. On the Intel x86, the -mstackrealign option generates an alternate prologue and epilogue that realigns the run-time stack if necessary. This supports mixing legacy codes that keep 4-byte stack alignment with modern codes that keep 16-byte stack alignment for SSE compatibility. See also the attribute "force_align_arg_pointer", applicable to individual functions.
-
-mpreferred-stack-boundary=num
-
Attempt to keep the stack boundary aligned to a 2 raised to num byte boundary. If -mpreferred-stack-boundary is not specified, the default is 4 (16 bytes or 128 bits).
Warning: When generating code for the x86-64 architecture with SSE extensions disabled, -mpreferred-stack-boundary=3 can be used to keep the stack boundary aligned to 8 byte boundary. Since x86-64 ABI require 16 byte stack alignment, this is ABI incompatible and intended to be used in controlled environment where stack space is important limitation. This option will lead to wrong code when functions compiled with 16 byte stack alignment (such as functions from a standard library) are called with misaligned stack. In this case, SSE instructions may lead to misaligned memory access traps. In addition, variable arguments will be handled incorrectly for 16 byte aligned objects (including x87 long double and __int128), leading to wrong results. You must build all modules with -mpreferred-stack-boundary=3, including any libraries. This includes the system libraries and startup modules.
-
-mincoming-stack-boundary=num
-
Assume the incoming stack is aligned to a 2 raised to num byte boundary. If -mincoming-stack-boundary is not specified, the one specified by -mpreferred-stack-boundary is used.
On Pentium and Pentium Pro, "double" and "long double" values should be aligned to an 8-byte boundary (see -malign-double) or suffer significant run time performance penalties. On Pentium III, the Streaming SIMD Extension (SSE) data type "__m128" may not work properly if it is not 16-byte aligned.
To ensure proper alignment of this values on the stack, the stack boundary must be as aligned as that required by any value stored on the stack. Further, every function must be generated such that it keeps the stack aligned. Thus calling a function compiled with a higher preferred stack boundary from a function compiled with a lower preferred stack boundary most likely misaligns the stack. It is recommended that libraries that use callbacks always use the default setting.
This extra alignment does consume extra stack space, and generally increases code size. Code that is sensitive to stack space usage, such as embedded systems and operating system kernels, may want to reduce the preferred alignment to -mpreferred-stack-boundary=2.
-
-mmmx
-
-
-mno-mmx
-
-
-msse
-
-
-mno-sse
-
-
-msse2
-
-
-mno-sse2
-
-
-msse3
-
-
-mno-sse3
-
-
-mssse3
-
-
-mno-ssse3
-
-
-msse4.1
-
-
-mno-sse4.1
-
-
-msse4.2
-
-
-mno-sse4.2
-
-
-msse4
-
-
-mno-sse4
-
-
-mavx
-
-
-mno-avx
-
-
-mavx2
-
-
-mno-avx2
-
-
-maes
-
-
-mno-aes
-
-
-mpclmul
-
-
-mno-pclmul
-
-
-mfsgsbase
-
-
-mno-fsgsbase
-
-
-mrdrnd
-
-
-mno-rdrnd
-
-
-mf16c
-
-
-mno-f16c
-
-
-mfma
-
-
-mno-fma
-
-
-msse4a
-
-
-mno-sse4a
-
-
-mfma4
-
-
-mno-fma4
-
-
-mxop
-
-
-mno-xop
-
-
-mlwp
-
-
-mno-lwp
-
-
-m3dnow
-
-
-mno-3dnow
-
-
-mpopcnt
-
-
-mno-popcnt
-
-
-mabm
-
-
-mno-abm
-
-
-mbmi
-
-
-mbmi2
-
-
-mno-bmi
-
-
-mno-bmi2
-
-
-mlzcnt
-
-
-mno-lzcnt
-
-
-mrtm
-
-
-mtbm
-
-
-mno-tbm
-
These switches enable or disable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, LZCNT, RTM or 3DNow! extended instruction sets. These extensions are also available as built-in functions: see X86 Built-in Functions, for details of the functions enabled and disabled by these switches.
To generate SSE/SSE2 instructions automatically from floating-point code (as opposed to 387 instructions), see -mfpmath=sse.
GCC depresses SSEx instructions when -mavx is used. Instead, it generates new AVX instructions or AVX equivalence for all SSEx instructions when needed.
These options enable GCC to use these extended instructions in generated code, even without -mfpmath=sse. Applications that perform run-time CPU detection must compile separate files for each supported architecture, using the appropriate flags. In particular, the file containing the CPU detection code should be compiled without these options.
-
-mcld
-
This option instructs GCC to emit a "cld" instruction in the prologue of functions that use string instructions. String instructions depend on the DF flag to select between autoincrement or autodecrement mode. While the ABI specifies the DF flag to be cleared on function entry, some operating systems violate this specification by not clearing the DF flag in their exception dispatchers. The exception handler can be invoked with the DF flag set, which leads to wrong direction mode when string instructions are used. This option can be enabled by default on 32-bit x86 targets by configuring GCC with the --enable-cld configure option. Generation of "cld" instructions can be suppressed with the -mno-cld compiler option in this case.
-
-mvzeroupper
-
This option instructs GCC to emit a "vzeroupper" instruction before a transfer of control flow out of the function to minimize the AVX to SSE transition penalty as well as remove unnecessary "zeroupper" intrinsics.
-
-mprefer-avx128
-
This option instructs GCC to use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
-
-mcx16
-
This option enables GCC to generate "CMPXCHG16B" instructions. "CMPXCHG16B" allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high-resolution counters that can be updated by multiple processors (or cores). This instruction is generated as part of atomic built-in functions: see __sync Builtins or __atomic Builtins for details.
-
-msahf
-
This option enables generation of "SAHF" instructions in 64-bit code. Early Intel Pentium 4 CPUs with Intel 64 support, prior to the introduction of Pentium 4 G1 step in December 2005, lacked the "LAHF" and "SAHF" instructions which were supported by AMD64. These are load and store instructions, respectively, for certain status flags. In 64-bit mode, the "SAHF" instruction is used to optimize "fmod", "drem", and "remainder" built-in functions; see Other Builtins for details.
-
-mmovbe
-
This option enables use of the "movbe" instruction to implement "__builtin_bswap32" and "__builtin_bswap64".
-
-mcrc32
-
This option enables built-in functions "__builtin_ia32_crc32qi", "__builtin_ia32_crc32hi", "__builtin_ia32_crc32si" and "__builtin_ia32_crc32di" to generate the "crc32" machine instruction.
-
-mrecip
-
This option enables use of "RCPSS" and "RSQRTSS" instructions (and their vectorized variants "RCPPS" and "RSQRTPS") with an additional Newton-Raphson step to increase precision instead of "DIVSS" and "SQRTSS" (and their vectorized variants) for single-precision floating-point arguments. These instructions are generated only when -funsafe-math-optimizations is enabled together with -finite-math-only and -fno-trapping-math. Note that while the throughput of the sequence is higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
Note that GCC implements "1.0f/sqrtf(x)" in terms of "RSQRTSS" (or "RSQRTPS") already with -ffast-math (or the above option combination), and doesn't need -mrecip.
Also note that GCC emits the above sequence with additional Newton-Raphson step for vectorized single-float division and vectorized "sqrtf( x)" already with -ffast-math (or the above option combination), and doesn't need -mrecip.
-
-mrecip=opt
-
This option controls which reciprocal estimate instructions may be used. opt is a comma-separated list of options, which may be preceded by a ! to invert the option:
-
all
-
Enable all estimate instructions.
-
default
-
Enable the default instructions, equivalent to -mrecip.
-
none
-
Disable all estimate instructions, equivalent to -mno-recip.
-
div
-
Enable the approximation for scalar division.
-
vec-div
-
Enable the approximation for vectorized division.
-
sqrt
-
Enable the approximation for scalar square root.
-
vec-sqrt
-
Enable the approximation for vectorized square root.
So, for example,
-mrecip=all,!sqrt enables all of the reciprocal approximations, except for square root.
-
-mveclibabi=type
-
Specifies the ABI type to use for vectorizing intrinsics using an external library. Supported values for type are svml for the Intel short vector math library and acml for the AMD math core library. To use this option, both -ftree-vectorize and -funsafe-math-optimizations have to be enabled, and an SVML or ACML ABI-compatible library must be specified at link time.
GCC currently emits calls to "vmldExp2", "vmldLn2", "vmldLog102", "vmldLog102", "vmldPow2", "vmldTanh2", "vmldTan2", "vmldAtan2", "vmldAtanh2", "vmldCbrt2", "vmldSinh2", "vmldSin2", "vmldAsinh2", "vmldAsin2", "vmldCosh2", "vmldCos2", "vmldAcosh2", "vmldAcos2", "vmlsExp4", "vmlsLn4", "vmlsLog104", "vmlsLog104", "vmlsPow4", "vmlsTanh4", "vmlsTan4", "vmlsAtan4", "vmlsAtanh4", "vmlsCbrt4", "vmlsSinh4", "vmlsSin4", "vmlsAsinh4", "vmlsAsin4", "vmlsCosh4", "vmlsCos4", "vmlsAcosh4" and "vmlsAcos4" for corresponding function type when -mveclibabi=svml is used, and "__vrd2_sin", "__vrd2_cos", "__vrd2_exp", "__vrd2_log", "__vrd2_log2", "__vrd2_log10", "__vrs4_sinf", "__vrs4_cosf", "__vrs4_expf", "__vrs4_logf", "__vrs4_log2f", "__vrs4_log10f" and "__vrs4_powf" for the corresponding function type when -mveclibabi=acml is used.
-
-mabi=name
-
Generate code for the specified calling convention. Permissible values are sysv for the ABI used on GNU/Linux and other systems, and ms for the Microsoft ABI. The default is to use the Microsoft ABI when targeting Microsoft Windows and the SysV ABI on all other systems. You can control this behavior for a specific function by using the function attribute ms_abi/sysv_abi.
-
-mtls-dialect=type
-
Generate code to access thread-local storage using the gnu or gnu2 conventions. gnu is the conservative default; gnu2 is more efficient, but it may add compile- and run-time requirements that cannot be satisfied on all systems.
-
-mpush-args
-
-
-mno-push-args
-
Use PUSH operations to store outgoing parameters. This method is shorter and usually equally fast as method using SUB/MOV operations and is enabled by default. In some cases disabling it may improve performance because of improved scheduling and reduced dependencies.
-
-maccumulate-outgoing-args
-
If enabled, the maximum amount of space required for outgoing arguments is computed in the function prologue. This is faster on most modern CPUs because of reduced dependencies, improved scheduling and reduced stack usage when the preferred stack boundary is not equal to 2. The drawback is a notable increase in code size. This switch implies -mno-push-args.
-
-mthreads
-
Support thread-safe exception handling on MinGW. Programs that rely on thread-safe exception handling must compile and link all code with the -mthreads option. When compiling, -mthreads defines "-D_MT"; when linking, it links in a special thread helper library -lmingwthrd which cleans up per-thread exception-handling data.
-
-mno-align-stringops
-
Do not align the destination of inlined string operations. This switch reduces code size and improves performance in case the destination is already aligned, but GCC doesn't know about it.
-
-minline-all-stringops
-
By default GCC inlines string operations only when the destination is known to be aligned to least a 4-byte boundary. This enables more inlining and increases code size, but may improve performance of code that depends on fast "memcpy", "strlen", and "memset" for short lengths.
-
-minline-stringops-dynamically
-
For string operations of unknown size, use run-time checks with inline code for small blocks and a library call for large blocks.
-
-mstringop-strategy=alg
-
Override the internal decision heuristic for the particular algorithm to use for inlining string operations. The allowed values for alg are:
-
rep_byte
-
-
rep_4byte
-
-
rep_8byte
-
Expand using i386 "rep" prefix of the specified size.
-
byte_loop
-
-
loop
-
-
unrolled_loop
-
Expand into an inline loop.
-
libcall
-
Always use a library call.
-
-momit-leaf-frame-pointer
-
Don't keep the frame pointer in a register for leaf functions. This avoids the instructions to save, set up, and restore frame pointers and makes an extra register available in leaf functions. The option -fomit-leaf-frame-pointer removes the frame pointer for leaf functions, which might make debugging harder.
-
-mtls-direct-seg-refs
-
-
-mno-tls-direct-seg-refs
-
Controls whether TLS variables may be accessed with offsets from the TLS segment register (%gs for 32-bit, %fs for 64-bit), or whether the thread base pointer must be added. Whether or not this is valid depends on the operating system, and whether it maps the segment to cover the entire TLS area.
For systems that use the GNU C Library, the default is on.
-
-msse2avx
-
-
-mno-sse2avx
-
Specify that the assembler should encode SSE instructions with VEX prefix. The option -mavx turns this on by default.
-
-mfentry
-
-
-mno-fentry
-
If profiling is active (-pg), put the profiling counter call before the prologue. Note: On x86 architectures the attribute "ms_hook_prologue" isn't possible at the moment for -mfentry and -pg.
-
-m8bit-idiv
-
-
-mno-8bit-idiv
-
On some processors, like Intel Atom, 8-bit unsigned integer divide is much faster than 32-bit/64-bit integer divide. This option generates a run-time check. If both dividend and divisor are within range of 0 to 255, 8-bit unsigned integer divide is used instead of 32-bit/64-bit integer divide.
-
-mavx256-split-unaligned-load
-
-
-mavx256-split-unaligned-store
-
Split 32-byte AVX unaligned load and store.
These -m switches are supported in addition to the above on x86-64 processors in 64-bit environments.
-
-m32
-
-
-m64
-
-
-mx32
-
Generate code for a 32-bit or 64-bit environment. The -m32 option sets "int", "long", and pointer types to 32 bits, and generates code that runs on any i386 system.
The -m64 option sets "int" to 32 bits and "long" and pointer types to 64 bits, and generates code for the x86-64 architecture. For Darwin only the -m64 option also turns off the -fno-pic and -mdynamic-no-pic options.
The -mx32 option sets "int", "long", and pointer types to 32 bits, and generates code for the x86-64 architecture.
-
-mno-red-zone
-
Do not use a so-called "red zone" for x86-64 code. The red zone is mandated by the x86-64 ABI; it is a 128-byte area beyond the location of the stack pointer that is not modified by signal or interrupt handlers and therefore can be used for temporary data without adjusting the stack pointer. The flag -mno-red-zone disables this red zone.
-
-mcmodel=small
-
Generate code for the small code model: the program and its symbols must be linked in the lower 2 GB of the address space. Pointers are 64 bits. Programs can be statically or dynamically linked. This is the default code model.
-
-mcmodel=kernel
-
Generate code for the kernel code model. The kernel runs in the negative 2 GB of the address space. This model has to be used for Linux kernel code.
-
-mcmodel=medium
-
Generate code for the medium model: the program is linked in the lower 2 GB of the address space. Small symbols are also placed there. Symbols with sizes larger than -mlarge-data-threshold are put into large data or BSS sections and can be located above 2GB. Programs can be statically or dynamically linked.
-
-mcmodel=large
-
Generate code for the large model. This model makes no assumptions about addresses and sizes of sections.
-
-maddress-mode=long
-
Generate code for long address mode. This is only supported for 64-bit and x32 environments. It is the default address mode for 64-bit environments.
-
-maddress-mode=short
-
Generate code for short address mode. This is only supported for 32-bit and x32 environments. It is the default address mode for 32-bit and x32 environments.
i386 and x86-64 Windows Options
These additional options are available for Microsoft Windows targets:
-
-mconsole
-
This option specifies that a console application is to be generated, by instructing the linker to set the PE header subsystem type required for console applications. This option is available for Cygwin and MinGW targets and is enabled by default on those targets.
-
-mdll
-
This option is available for Cygwin and MinGW targets. It specifies that a DLL---a dynamic link library---is to be generated, enabling the selection of the required runtime startup object and entry point.
-
-mnop-fun-dllimport
-
This option is available for Cygwin and MinGW targets. It specifies that the "dllimport" attribute should be ignored.
-
-mthread
-
This option is available for MinGW targets. It specifies that MinGW-specific thread support is to be used.
-
-municode
-
This option is available for MinGW-w64 targets. It causes the "UNICODE" preprocessor macro to be predefined, and chooses Unicode-capable runtime startup code.
-
-mwin32
-
This option is available for Cygwin and MinGW targets. It specifies that the typical Microsoft Windows predefined macros are to be set in the pre-processor, but does not influence the choice of runtime library/startup code.
-
-mwindows
-
This option is available for Cygwin and MinGW targets. It specifies that a GUI application is to be generated by instructing the linker to set the PE header subsystem type appropriately.
-
-fno-set-stack-executable
-
This option is available for MinGW targets. It specifies that the executable flag for the stack used by nested functions isn't set. This is necessary for binaries running in kernel mode of Microsoft Windows, as there the User32 API, which is used to set executable privileges, isn't available.
-
-fwritable-relocated-rdata
-
This option is available for MinGW and Cygwin targets. It specifies that relocated-data in read-only section is put into .data section. This is a necessary for older runtimes not supporting modification of .rdata sections for pseudo-relocation.
-
-mpe-aligned-commons
-
This option is available for Cygwin and MinGW targets. It specifies that the GNU extension to the PE file format that permits the correct alignment of COMMON variables should be used when generating code. It is enabled by default if GCC detects that the target assembler found during configuration supports the feature.
See also under i386 and x86-64 Options for standard options.
IA-64 Options
These are the -m options defined for the Intel IA-64 architecture.
-
-mbig-endian
-
Generate code for a big-endian target. This is the default for HP-UX.
-
-mlittle-endian
-
Generate code for a little-endian target. This is the default for AIX5 and GNU/Linux.
-
-mgnu-as
-
-
-mno-gnu-as
-
Generate (or don't) code for the GNU assembler. This is the default.
-
-mgnu-ld
-
-
-mno-gnu-ld
-
Generate (or don't) code for the GNU linker. This is the default.
-
-mno-pic
-
Generate code that does not use a global pointer register. The result is not position independent code, and violates the IA-64 ABI.
-
-mvolatile-asm-stop
-
-
-mno-volatile-asm-stop
-
Generate (or don't) a stop bit immediately before and after volatile asm statements.
-
-mregister-names
-
-
-mno-register-names
-
Generate (or don't) in, loc, and out register names for the stacked registers. This may make assembler output more readable.
-
-mno-sdata
-
-
-msdata
-
Disable (or enable) optimizations that use the small data section. This may be useful for working around optimizer bugs.
-
-mconstant-gp
-
Generate code that uses a single constant global pointer value. This is useful when compiling kernel code.
-
-mauto-pic
-
Generate code that is self-relocatable. This implies -mconstant-gp. This is useful when compiling firmware code.
-
-minline-float-divide-min-latency
-
Generate code for inline divides of floating-point values using the minimum latency algorithm.
-
-minline-float-divide-max-throughput
-
Generate code for inline divides of floating-point values using the maximum throughput algorithm.
-
-mno-inline-float-divide
-
Do not generate inline code for divides of floating-point values.
-
-minline-int-divide-min-latency
-
Generate code for inline divides of integer values using the minimum latency algorithm.
-
-minline-int-divide-max-throughput
-
Generate code for inline divides of integer values using the maximum throughput algorithm.
-
-mno-inline-int-divide
-
Do not generate inline code for divides of integer values.
-
-minline-sqrt-min-latency
-
Generate code for inline square roots using the minimum latency algorithm.
-
-minline-sqrt-max-throughput
-
Generate code for inline square roots using the maximum throughput algorithm.
-
-mno-inline-sqrt
-
Do not generate inline code for "sqrt".
-
-mfused-madd
-
-
-mno-fused-madd
-
Do (don't) generate code that uses the fused multiply/add or multiply/subtract instructions. The default is to use these instructions.
-
-mno-dwarf2-asm
-
-
-mdwarf2-asm
-
Don't (or do) generate assembler code for the DWARF 2 line number debugging info. This may be useful when not using the GNU assembler.
-
-mearly-stop-bits
-
-
-mno-early-stop-bits
-
Allow stop bits to be placed earlier than immediately preceding the instruction that triggered the stop bit. This can improve instruction scheduling, but does not always do so.
-
-mfixed-range=register-range
-
Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.
-
-mtls-size=tls-size
-
Specify bit size of immediate TLS offsets. Valid values are 14, 22, and 64.
-
-mtune=cpu-type
-
Tune the instruction scheduling for a particular CPU, Valid values are itanium, itanium1, merced, itanium2, and mckinley.
-
-milp32
-
-
-mlp64
-
Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits. These are HP-UX specific flags.
-
-mno-sched-br-data-spec
-
-
-msched-br-data-spec
-
(Dis/En)able data speculative scheduling before reload. This results in generation of "ld.a" instructions and the corresponding check instructions ("ld.c" / "chk.a"). The default is 'disable'.
-
-msched-ar-data-spec
-
-
-mno-sched-ar-data-spec
-
(En/Dis)able data speculative scheduling after reload. This results in generation of "ld.a" instructions and the corresponding check instructions ("ld.c" / "chk.a"). The default is 'enable'.
-
-mno-sched-control-spec
-
-
-msched-control-spec
-
(Dis/En)able control speculative scheduling. This feature is available only during region scheduling (i.e. before reload). This results in generation of the "ld.s" instructions and the corresponding check instructions "chk.s". The default is 'disable'.
-
-msched-br-in-data-spec
-
-
-mno-sched-br-in-data-spec
-
(En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads before reload. This is effective only with -msched-br-data-spec enabled. The default is 'enable'.
-
-msched-ar-in-data-spec
-
-
-mno-sched-ar-in-data-spec
-
(En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads after reload. This is effective only with -msched-ar-data-spec enabled. The default is 'enable'.
-
-msched-in-control-spec
-
-
-mno-sched-in-control-spec
-
(En/Dis)able speculative scheduling of the instructions that are dependent on the control speculative loads. This is effective only with -msched-control-spec enabled. The default is 'enable'.
-
-mno-sched-prefer-non-data-spec-insns
-
-
-msched-prefer-non-data-spec-insns
-
If enabled, data-speculative instructions are chosen for schedule only if there are no other choices at the moment. This makes the use of the data speculation much more conservative. The default is 'disable'.
-
-mno-sched-prefer-non-control-spec-insns
-
-
-msched-prefer-non-control-spec-insns
-
If enabled, control-speculative instructions are chosen for schedule only if there are no other choices at the moment. This makes the use of the control speculation much more conservative. The default is 'disable'.
-
-mno-sched-count-spec-in-critical-path
-
-
-msched-count-spec-in-critical-path
-
If enabled, speculative dependencies are considered during computation of the instructions priorities. This makes the use of the speculation a bit more conservative. The default is 'disable'.
-
-msched-spec-ldc
-
Use a simple data speculation check. This option is on by default.
-
-msched-control-spec-ldc
-
Use a simple check for control speculation. This option is on by default.
-
-msched-stop-bits-after-every-cycle
-
Place a stop bit after every cycle when scheduling. This option is on by default.
-
-msched-fp-mem-deps-zero-cost
-
Assume that floating-point stores and loads are not likely to cause a conflict when placed into the same instruction group. This option is disabled by default.
-
-msel-sched-dont-check-control-spec
-
Generate checks for control speculation in selective scheduling. This flag is disabled by default.
-
-msched-max-memory-insns=max-insns
-
Limit on the number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same instruction group. Frequently useful to prevent cache bank conflicts. The default value is 1.
-
-msched-max-memory-insns-hard-limit
-
Makes the limit specified by msched-max-memory-insns a hard limit, disallowing more than that number in an instruction group. Otherwise, the limit is "soft", meaning that non-memory operations are preferred when the limit is reached, but memory operations may still be scheduled.
LM32 Options
These -m options are defined for the LatticeMico32 architecture:
-
-mbarrel-shift-enabled
-
Enable barrel-shift instructions.
-
-mdivide-enabled
-
Enable divide and modulus instructions.
-
-mmultiply-enabled
-
Enable multiply instructions.
-
-msign-extend-enabled
-
Enable sign extend instructions.
-
-muser-enabled
-
Enable user-defined instructions.
M32C Options
-
-mcpu=name
-
Select the CPU for which code is generated. name may be one of r8c for the R8C/Tiny series, m16c for the M16C (up to /60) series, m32cm for the M16C/80 series, or m32c for the M32C/80 series.
-
-msim
-
Specifies that the program will be run on the simulator. This causes an alternate runtime library to be linked in which supports, for example, file I/O. You must not use this option when generating programs that will run on real hardware; you must provide your own runtime library for whatever I/O functions are needed.
-
-memregs=number
-
Specifies the number of memory-based pseudo-registers GCC uses during code generation. These pseudo-registers are used like real registers, so there is a tradeoff between GCC's ability to fit the code into available registers, and the performance penalty of using memory instead of registers. Note that all modules in a program must be compiled with the same value for this option. Because of that, you must not use this option with GCC's default runtime libraries.
M32R/D Options
These -m options are defined for Renesas M32R/D architectures:
-
-m32r2
-
Generate code for the M32R/2.
-
-m32rx
-
Generate code for the M32R/X.
-
-m32r
-
Generate code for the M32R. This is the default.
-
-mmodel=small
-
Assume all objects live in the lower 16MB of memory (so that their addresses can be loaded with the "ld24" instruction), and assume all subroutines are reachable with the "bl" instruction. This is the default.
The addressability of a particular object can be set with the "model" attribute.
-
-mmodel=medium
-
Assume objects may be anywhere in the 32-bit address space (the compiler generates "seth/add3" instructions to load their addresses), and assume all subroutines are reachable with the "bl" instruction.
-
-mmodel=large
-
Assume objects may be anywhere in the 32-bit address space (the compiler generates "seth/add3" instructions to load their addresses), and assume subroutines may not be reachable with the "bl" instruction (the compiler generates the much slower "seth/add3/jl" instruction sequence).
-
-msdata=none
-
Disable use of the small data area. Variables are put into one of .data, .bss, or .rodata (unless the "section" attribute has been specified). This is the default.
The small data area consists of sections .sdata and .sbss. Objects may be explicitly put in the small data area with the "section" attribute using one of these sections.
-
-msdata=sdata
-
Put small global and static data in the small data area, but do not generate special code to reference them.
-
-msdata=use
-
Put small global and static data in the small data area, and generate special instructions to reference them.
-
-G num
-
Put global and static objects less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS sections. The default value of num is 8. The -msdata option must be set to one of sdata or use for this option to have any effect.
All modules should be compiled with the same -G num value. Compiling with different values of num may or may not work; if it doesn't the linker gives an error message---incorrect code is not generated.
-
-mdebug
-
Makes the M32R-specific code in the compiler display some statistics that might help in debugging programs.
-
-malign-loops
-
Align all loops to a 32-byte boundary.
-
-mno-align-loops
-
Do not enforce a 32-byte alignment for loops. This is the default.
-
-missue-rate=number
-
Issue number instructions per cycle. number can only be 1 or 2.
-
-mbranch-cost=number
-
number can only be 1 or 2. If it is 1 then branches are preferred over conditional code, if it is 2, then the opposite applies.
-
-mflush-trap=number
-
Specifies the trap number to use to flush the cache. The default is 12. Valid numbers are between 0 and 15 inclusive.
-
-mno-flush-trap
-
Specifies that the cache cannot be flushed by using a trap.
-
-mflush-func=name
-
Specifies the name of the operating system function to call to flush the cache. The default is _flush_cache, but a function call is only used if a trap is not available.
-
-mno-flush-func
-
Indicates that there is no OS function for flushing the cache.
M680x0 Options
These are the -m options defined for M680x0 and ColdFire processors. The default settings depend on which architecture was selected when the compiler was configured; the defaults for the most common choices are given below.
-
-march=arch
-
Generate code for a specific M680x0 or ColdFire instruction set architecture. Permissible values of arch for M680x0 architectures are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32. ColdFire architectures are selected according to Freescale's ISA classification and the permissible values are: isaa, isaaplus, isab and isac.
GCC defines a macro __mcfarch__ whenever it is generating code for a ColdFire target. The arch in this macro is one of the -march arguments given above.
When used together, -march and -mtune select code that runs on a family of similar processors but that is optimized for a particular microarchitecture.
-
-mcpu=cpu
-
Generate code for a specific M680x0 or ColdFire processor. The M680x0 cpus are: 68000, 68010, 68020, 68030, 68040, 68060, 68302, 68332 and cpu32. The ColdFire cpus are given by the table below, which also classifies the CPUs into families:
-
Family : -mcpu arguments
-
-
51 : 51 51ac 51ag 51cn 51em 51je 51jf 51jg 51jm 51mm 51qe 51qm
-
-
5206 : 5202 5204 5206
-
-
5206e : 5206e
-
-
5208 : 5207 5208
-
-
5211a : 5210a 5211a
-
-
5213 : 5211 5212 5213
-
-
5216 : 5214 5216
-
-
52235 : 52230 52231 52232 52233 52234 52235
-
-
5225 : 5224 5225
-
-
52259 : 52252 52254 52255 52256 52258 52259
-
-
5235 : 5232 5233 5234 5235 523x
-
-
5249 : 5249
-
-
5250 : 5250
-
-
5271 : 5270 5271
-
-
5272 : 5272
-
-
5275 : 5274 5275
-
-
5282 : 5280 5281 5282 528x
-
-
53017 : 53011 53012 53013 53014 53015 53016 53017
-
-
5307 : 5307
-
-
5329 : 5327 5328 5329 532x
-
-
5373 : 5372 5373 537x
-
-
5407 : 5407
-
-
5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485
-
-mcpu=cpu overrides
-march=arch if
arch is compatible with
cpu. Other combinations of
-mcpu and
-march are rejected.
GCC defines the macro
__mcf_cpu_cpu when ColdFire target
cpu is selected. It also defines
__mcf_family_family, where the value of
family is given by the table above.
-
-mtune=tune
-
Tune the code for a particular microarchitecture within the constraints set by -march and -mcpu. The M680x0 microarchitectures are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32. The ColdFire microarchitectures are: cfv1, cfv2, cfv3, cfv4 and cfv4e.
You can also use -mtune=68020-40 for code that needs to run relatively well on 68020, 68030 and 68040 targets. -mtune=68020-60 is similar but includes 68060 targets as well. These two options select the same tuning decisions as -m68020-40 and -m68020-60 respectively.
GCC defines the macros __mcarch and __mcarch__ when tuning for 680x0 architecture arch. It also defines mcarch unless either -ansi or a non-GNU -std option is used. If GCC is tuning for a range of architectures, as selected by -mtune=68020-40 or -mtune=68020-60, it defines the macros for every architecture in the range.
GCC also defines the macro __muarch__ when tuning for ColdFire microarchitecture uarch, where uarch is one of the arguments given above.
-
-m68000
-
-
-mc68000
-
Generate output for a 68000. This is the default when the compiler is configured for 68000-based systems. It is equivalent to -march=68000.
Use this option for microcontrollers with a 68000 or EC000 core, including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
-
-m68010
-
Generate output for a 68010. This is the default when the compiler is configured for 68010-based systems. It is equivalent to -march=68010.
-
-m68020
-
-
-mc68020
-
Generate output for a 68020. This is the default when the compiler is configured for 68020-based systems. It is equivalent to -march=68020.
-
-m68030
-
Generate output for a 68030. This is the default when the compiler is configured for 68030-based systems. It is equivalent to -march=68030.
-
-m68040
-
Generate output for a 68040. This is the default when the compiler is configured for 68040-based systems. It is equivalent to -march=68040.
This option inhibits the use of 68881/68882 instructions that have to be emulated by software on the 68040. Use this option if your 68040 does not have code to emulate those instructions.
-
-m68060
-
Generate output for a 68060. This is the default when the compiler is configured for 68060-based systems. It is equivalent to -march=68060.
This option inhibits the use of 68020 and 68881/68882 instructions that have to be emulated by software on the 68060. Use this option if your 68060 does not have code to emulate those instructions.
-
-mcpu32
-
Generate output for a CPU32. This is the default when the compiler is configured for CPU32-based systems. It is equivalent to -march=cpu32.
Use this option for microcontrollers with a CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, 68336, 68340, 68341, 68349 and 68360.
-
-m5200
-
Generate output for a 520X ColdFire CPU. This is the default when the compiler is configured for 520X-based systems. It is equivalent to -mcpu=5206, and is now deprecated in favor of that option.
Use this option for microcontroller with a 5200 core, including the MCF5202, MCF5203, MCF5204 and MCF5206.
-
-m5206e
-
Generate output for a 5206e ColdFire CPU. The option is now deprecated in favor of the equivalent -mcpu=5206e.
-
-m528x
-
Generate output for a member of the ColdFire 528X family. The option is now deprecated in favor of the equivalent -mcpu=528x.
-
-m5307
-
Generate output for a ColdFire 5307 CPU. The option is now deprecated in favor of the equivalent -mcpu=5307.
-
-m5407
-
Generate output for a ColdFire 5407 CPU. The option is now deprecated in favor of the equivalent -mcpu=5407.
-
-mcfv4e
-
Generate output for a ColdFire V4e family CPU (e.g. 547x/548x). This includes use of hardware floating-point instructions. The option is equivalent to -mcpu=547x, and is now deprecated in favor of that option.
-
-m68020-40
-
Generate output for a 68040, without using any of the new instructions. This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68040.
The option is equivalent to -march=68020 -mtune=68020-40.
-
-m68020-60
-
Generate output for a 68060, without using any of the new instructions. This results in code that can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68060.
The option is equivalent to -march=68020 -mtune=68020-60.
-
-mhard-float
-
-
-m68881
-
Generate floating-point instructions. This is the default for 68020 and above, and for ColdFire devices that have an FPU. It defines the macro __HAVE_68881__ on M680x0 targets and __mcffpu__ on ColdFire targets.
-
-msoft-float
-
Do not generate floating-point instructions; use library calls instead. This is the default for 68000, 68010, and 68832 targets. It is also the default for ColdFire devices that have no FPU.
-
-mdiv
-
-
-mno-div
-
Generate (do not generate) ColdFire hardware divide and remainder instructions. If -march is used without -mcpu, the default is "on" for ColdFire architectures and "off" for M680x0 architectures. Otherwise, the default is taken from the target CPU (either the default CPU, or the one specified by -mcpu). For example, the default is "off" for -mcpu=5206 and "on" for -mcpu=5206e.
GCC defines the macro __mcfhwdiv__ when this option is enabled.
-
-mshort
-
Consider type "int" to be 16 bits wide, like "short int". Additionally, parameters passed on the stack are also aligned to a 16-bit boundary even on targets whose API mandates promotion to 32-bit.
-
-mno-short
-
Do not consider type "int" to be 16 bits wide. This is the default.
-
-mnobitfield
-
-
-mno-bitfield
-
Do not use the bit-field instructions. The -m68000, -mcpu32 and -m5200 options imply -mnobitfield.
-
-mbitfield
-
Do use the bit-field instructions. The -m68020 option implies -mbitfield. This is the default if you use a configuration designed for a 68020.
-
-mrtd
-
Use a different function-calling convention, in which functions that take a fixed number of arguments return with the "rtd" instruction, which pops their arguments while returning. This saves one instruction in the caller since there is no need to pop the arguments there.
This calling convention is incompatible with the one normally used on Unix, so you cannot use it if you need to call libraries compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that take variable numbers of arguments (including "printf"); otherwise incorrect code is generated for calls to those functions.
In addition, seriously incorrect code results if you call a function with too many arguments. (Normally, extra arguments are harmlessly ignored.)
The "rtd" instruction is supported by the 68010, 68020, 68030, 68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
-
-mno-rtd
-
Do not use the calling conventions selected by -mrtd. This is the default.
-
-malign-int
-
-
-mno-align-int
-
Control whether GCC aligns "int", "long", "long long", "float", "double", and "long double" variables on a 32-bit boundary ( -malign-int) or a 16-bit boundary (-mno-align-int). Aligning variables on 32-bit boundaries produces code that runs somewhat faster on processors with 32-bit busses at the expense of more memory.
Warning: if you use the -malign-int switch, GCC aligns structures containing the above types differently than most published application binary interface specifications for the m68k.
-
-mpcrel
-
Use the pc-relative addressing mode of the 68000 directly, instead of using a global offset table. At present, this option implies -fpic, allowing at most a 16-bit offset for pc-relative addressing. -fPIC is not presently supported with -mpcrel, though this could be supported for 68020 and higher processors.
-
-mno-strict-align
-
-
-mstrict-align
-
Do not (do) assume that unaligned memory references are handled by the system.
-
-msep-data
-
Generate code that allows the data segment to be located in a different area of memory from the text segment. This allows for execute-in-place in an environment without virtual memory management. This option implies -fPIC.
-
-mno-sep-data
-
Generate code that assumes that the data segment follows the text segment. This is the default.
-
-mid-shared-library
-
Generate code that supports shared libraries via the library ID method. This allows for execute-in-place and shared libraries in an environment without virtual memory management. This option implies -fPIC.
-
-mno-id-shared-library
-
Generate code that doesn't assume ID-based shared libraries are being used. This is the default.
-
-mshared-library-id=n
-
Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0 generates more compact code; specifying other values forces the allocation of that number to the current library, but is no more space- or time-efficient than omitting this option.
-
-mxgot
-
-
-mno-xgot
-
When generating position-independent code for ColdFire, generate code that works if the GOT has more than 8192 entries. This code is larger and slower than code generated without this option. On M680x0 processors, this option is not needed; -fPIC suffices.
GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as:
relocation truncated to fit: R_68K_GOT16O foobar
If this happens, you should recompile your code with -mxgot. It should then work with very large GOTs. However, code generated with -mxgot is less efficient, since it takes 4 instructions to fetch the value of a global symbol.
Note that some linkers, including newer versions of the GNU linker, can create multiple GOTs and sort GOT entries. If you have such a linker, you should only need to use -mxgot when compiling a single object file that accesses more than 8192 GOT entries. Very few do.
These options have no effect unless GCC is generating position-independent code.
MCore Options
These are the -m options defined for the Motorola M*Core processors.
-
-mhardlit
-
-
-mno-hardlit
-
Inline constants into the code stream if it can be done in two instructions or less.
-
-mdiv
-
-
-mno-div
-
Use the divide instruction. (Enabled by default).
-
-mrelax-immediate
-
-
-mno-relax-immediate
-
Allow arbitrary-sized immediates in bit operations.
-
-mwide-bitfields
-
-
-mno-wide-bitfields
-
Always treat bit-fields as "int"-sized.
-
-m4byte-functions
-
-
-mno-4byte-functions
-
Force all functions to be aligned to a 4-byte boundary.
-
-mcallgraph-data
-
-
-mno-callgraph-data
-
Emit callgraph information.
-
-mslow-bytes
-
-
-mno-slow-bytes
-
Prefer word access when reading byte quantities.
-
-mlittle-endian
-
-
-mbig-endian
-
Generate code for a little-endian target.
-
-m210
-
-
-m340
-
Generate code for the 210 processor.
-
-mno-lsim
-
Assume that runtime support has been provided and so omit the simulator library ( libsim.a) from the linker command line.
-
-mstack-increment=size
-
Set the maximum amount for a single stack increment operation. Large values can increase the speed of programs that contain functions that need a large amount of stack space, but they can also trigger a segmentation fault if the stack is extended too much. The default value is 0x1000.
MeP Options
-
-mabsdiff
-
Enables the "abs" instruction, which is the absolute difference between two registers.
-
-mall-opts
-
Enables all the optional instructions---average, multiply, divide, bit operations, leading zero, absolute difference, min/max, clip, and saturation.
-
-maverage
-
Enables the "ave" instruction, which computes the average of two registers.
-
-mbased=n
-
Variables of size n bytes or smaller are placed in the ".based" section by default. Based variables use the $tp register as a base register, and there is a 128-byte limit to the ".based" section.
-
-mbitops
-
Enables the bit operation instructions---bit test ("btstm"), set ("bsetm"), clear ("bclrm"), invert ("bnotm"), and test-and-set ("tas").
-
-mc=name
-
Selects which section constant data is placed in. name may be "tiny", "near", or "far".
-
-mclip
-
Enables the "clip" instruction. Note that "-mclip" is not useful unless you also provide "-mminmax".
-
-mconfig=name
-
Selects one of the built-in core configurations. Each MeP chip has one or more modules in it; each module has a core CPU and a variety of coprocessors, optional instructions, and peripherals. The "MeP-Integrator" tool, not part of GCC, provides these configurations through this option; using this option is the same as using all the corresponding command-line options. The default configuration is "default".
-
-mcop
-
Enables the coprocessor instructions. By default, this is a 32-bit coprocessor. Note that the coprocessor is normally enabled via the "-mconfig=" option.
-
-mcop32
-
Enables the 32-bit coprocessor's instructions.
-
-mcop64
-
Enables the 64-bit coprocessor's instructions.
-
-mivc2
-
Enables IVC2 scheduling. IVC2 is a 64-bit VLIW coprocessor.
-
-mdc
-
Causes constant variables to be placed in the ".near" section.
-
-mdiv
-
Enables the "div" and "divu" instructions.
-
-meb
-
Generate big-endian code.
-
-mel
-
Generate little-endian code.
-
-mio-volatile
-
Tells the compiler that any variable marked with the "io" attribute is to be considered volatile.
-
-ml
-
Causes variables to be assigned to the ".far" section by default.
-
-mleadz
-
Enables the "leadz" (leading zero) instruction.
-
-mm
-
Causes variables to be assigned to the ".near" section by default.
-
-mminmax
-
Enables the "min" and "max" instructions.
-
-mmult
-
Enables the multiplication and multiply-accumulate instructions.
-
-mno-opts
-
Disables all the optional instructions enabled by "-mall-opts".
-
-mrepeat
-
Enables the "repeat" and "erepeat" instructions, used for low-overhead looping.
-
-ms
-
Causes all variables to default to the ".tiny" section. Note that there is a 65536-byte limit to this section. Accesses to these variables use the %gp base register.
-
-msatur
-
Enables the saturation instructions. Note that the compiler does not currently generate these itself, but this option is included for compatibility with other tools, like "as".
-
-msdram
-
Link the SDRAM-based runtime instead of the default ROM-based runtime.
-
-msim
-
Link the simulator runtime libraries.
-
-msimnovec
-
Link the simulator runtime libraries, excluding built-in support for reset and exception vectors and tables.
-
-mtf
-
Causes all functions to default to the ".far" section. Without this option, functions default to the ".near" section.
-
-mtiny=n
-
Variables that are n bytes or smaller are allocated to the ".tiny" section. These variables use the $gp base register. The default for this option is 4, but note that there's a 65536-byte limit to the ".tiny" section.
MicroBlaze Options
-
-msoft-float
-
Use software emulation for floating point (default).
-
-mhard-float
-
Use hardware floating-point instructions.
-
-mmemcpy
-
Do not optimize block moves, use "memcpy".
-
-mno-clearbss
-
This option is deprecated. Use -fno-zero-initialized-in-bss instead.
-
-mcpu=cpu-type
-
Use features of, and schedule code for, the given CPU. Supported values are in the format vX.YY.Z, where X is a major version, YY is the minor version, and Z is compatibility code. Example values are v3.00.a, v4.00.b, v5.00.a, v5.00.b, v5.00.b, v6.00.a.
-
-mxl-soft-mul
-
Use software multiply emulation (default).
-
-mxl-soft-div
-
Use software emulation for divides (default).
-
-mxl-barrel-shift
-
Use the hardware barrel shifter.
-
-mxl-pattern-compare
-
Use pattern compare instructions.
-
-msmall-divides
-
Use table lookup optimization for small signed integer divisions.
-
-mxl-stack-check
-
This option is deprecated. Use -fstack-check instead.
-
-mxl-gp-opt
-
Use GP-relative ".sdata"/".sbss" sections.
-
-mxl-multiply-high
-
Use multiply high instructions for high part of 32x32 multiply.
-
-mxl-float-convert
-
Use hardware floating-point conversion instructions.
-
-mxl-float-sqrt
-
Use hardware floating-point square root instruction.
-
-mbig-endian
-
Generate code for a big-endian target.
-
-mlittle-endian
-
Generate code for a little-endian target.
-
-mxl-reorder
-
Use reorder instructions (swap and byte reversed load/store).
-
-mxl-mode-app-model
-
Select application model app-model. Valid models are
-
executable
-
normal executable (default), uses startup code crt0.o.
-
xmdstub
-
for use with Xilinx Microprocessor Debugger (XMD) based software intrusive debug agent called xmdstub. This uses startup file crt1.o and sets the start address of the program to 0x800.
-
bootstrap
-
for applications that are loaded using a bootloader. This model uses startup file crt2.o which does not contain a processor reset vector handler. This is suitable for transferring control on a processor reset to the bootloader rather than the application.
-
novectors
-
for applications that do not require any of the MicroBlaze vectors. This option may be useful for applications running within a monitoring application. This model uses crt3.o as a startup file.
Option
-xl-mode-app-model is a deprecated alias for
-mxl-mode-app-model.
MIPS Options
-
-EB
-
Generate big-endian code.
-
-EL
-
Generate little-endian code. This is the default for mips*el-*-* configurations.
-
-march=arch
-
Generate code that runs on arch, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: mips1, mips2, mips3, mips4, mips32, mips32r2, mips64 and mips64r2. The processor names are: 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, 5kc, 5kf, 20kc, 24kc, 24kf2_1, 24kf1_1, 24kec, 24kef2_1, 24kef1_1, 34kc, 34kf2_1, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf1_1, loongson2e, loongson2f, loongson3a, m4k, octeon, octeon+, octeon2, orion, r2000, r3000, r3900, r4000, r4400, r4600, r4650, r4700, r6000, r8000, rm7000, rm9000, r10000, r12000, r14000, r16000, sb1, sr71000, vr4100, vr4111, vr4120, vr4130, vr4300, vr5000, vr5400, vr5500, xlr and xlp. The special value from-abi selects the most compatible architecture for the selected ABI (that is, mips1 for 32-bit ABIs and mips3 for 64-bit ABIs).
The native Linux/GNU toolchain also supports the value native, which selects the best architecture option for the host processor. -march=native has no effect if GCC does not recognize the processor.
In processor names, a final 000 can be abbreviated as k (for example, -march=r2k). Prefixes are optional, and vr may be written r.
Names of the form nf2_1 refer to processors with FPUs clocked at half the rate of the core, names of the form nf1_1 refer to processors with FPUs clocked at the same rate as the core, and names of the form nf3_2 refer to processors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, nf is accepted as a synonym for nf2_1 while nx and bfx are accepted as synonyms for nf1_1.
GCC defines two macros based on the value of this option. The first is _MIPS_ARCH, which gives the name of target architecture, as a string. The second has the form _MIPS_ARCH_foo, where foo is the capitalized value of _MIPS_ARCH. For example, -march=r2000 sets _MIPS_ARCH to "r2000" and defines the macro _MIPS_ARCH_R2000.
Note that the _MIPS_ARCH macro uses the processor names given above. In other words, it has the full prefix and does not abbreviate 000 as k. In the case of from-abi, the macro names the resolved architecture (either "mips1" or "mips3"). It names the default architecture when no -march option is given.
-
-mtune=arch
-
Optimize for arch. Among other things, this option controls the way instructions are scheduled, and the perceived cost of arithmetic operations. The list of arch values is the same as for -march.
When this option is not used, GCC optimizes for the processor specified by -march. By using -march and -mtune together, it is possible to generate code that runs on a family of processors, but optimize the code for one particular member of that family.
-mtune defines the macros _MIPS_TUNE and _MIPS_TUNE_foo, which work in the same way as the -march ones described above.
-
-mips1
-
Equivalent to -march=mips1.
-
-mips2
-
Equivalent to -march=mips2.
-
-mips3
-
Equivalent to -march=mips3.
-
-mips4
-
Equivalent to -march=mips4.
-
-mips32
-
Equivalent to -march=mips32.
-
-mips32r2
-
Equivalent to -march=mips32r2.
-
-mips64
-
Equivalent to -march=mips64.
-
-mips64r2
-
Equivalent to -march=mips64r2.
-
-mips16
-
-
-mno-mips16
-
Generate (do not generate) MIPS16 code. If GCC is targeting a MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE.
MIPS16 code generation can also be controlled on a per-function basis by means of "mips16" and "nomips16" attributes.
-
-mflip-mips16
-
Generate MIPS16 code on alternating functions. This option is provided for regression testing of mixed MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code.
-
-minterlink-mips16
-
-
-mno-interlink-mips16
-
Require (do not require) that non-MIPS16 code be link-compatible with MIPS16 code.
For example, non-MIPS16 code cannot jump directly to MIPS16 code; it must either use a call or an indirect jump. -minterlink-mips16 therefore disables direct jumps unless GCC knows that the target of the jump is not MIPS16.
-
-mabi=32
-
-
-mabi=o64
-
-
-mabi=n32
-
-
-mabi=64
-
-
-mabi=eabi
-
Generate code for the given ABI.
Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 64-bit architecture, but you can use -mgp32 to get 32-bit code instead.
For information about the O64 ABI, see < http://gcc.gnu.org/projects/mipso64-abi.html>.
GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with -mabi=32 -mfp64. This ABI relies on the "mthc1" and "mfhc1" instructions and is therefore only supported for MIPS32R2 processors.
The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in $f0 only, not a $f0/$f1 pair. The set of call-saved registers also remains the same, but all 64 bits are saved.
-
-mabicalls
-
-
-mno-abicalls
-
Generate (do not generate) code that is suitable for SVR4-style dynamic objects. -mabicalls is the default for SVR4-based systems.
-
-mshared
-
-
-mno-shared
-
Generate (do not generate) code that is fully position-independent, and that can therefore be linked into shared libraries. This option only affects -mabicalls.
All -mabicalls code has traditionally been position-independent, regardless of options like -fPIC and -fpic. However, as an extension, the GNU toolchain allows executables to use absolute accesses for locally-binding symbols. It can also use shorter GP initialization sequences and generate direct calls to locally-defined functions. This mode is selected by -mno-shared.
-mno-shared depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU linker. However, the option does not affect the ABI of the final executable; it only affects the ABI of relocatable objects. Using -mno-shared generally makes executables both smaller and quicker.
-mshared is the default.
-
-mplt
-
-
-mno-plt
-
Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option only affects -mno-shared -mabicalls. For the n64 ABI, this option has no effect without -msym32.
You can make -mplt the default by configuring GCC with --with-mips-plt. The default is -mno-plt otherwise.
-
-mxgot
-
-
-mno-xgot
-
Lift (do not lift) the usual restrictions on the size of the global offset table.
GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such as:
relocation truncated to fit: R_MIPS_GOT16 foobar
If this happens, you should recompile your code with -mxgot. This works with very large GOTs, although the code is also less efficient, since it takes three instructions to fetch the value of a global symbol.
Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use -mxgot when a single object file accesses more than 64k's worth of GOT entries. Very few do.
These options have no effect unless GCC is generating position independent code.
-
-mgp32
-
Assume that general-purpose registers are 32 bits wide.
-
-mgp64
-
Assume that general-purpose registers are 64 bits wide.
-
-mfp32
-
Assume that floating-point registers are 32 bits wide.
-
-mfp64
-
Assume that floating-point registers are 64 bits wide.
-
-mhard-float
-
Use floating-point coprocessor instructions.
-
-msoft-float
-
Do not use floating-point coprocessor instructions. Implement floating-point calculations using library calls instead.
-
-mno-float
-
Equivalent to -msoft-float, but additionally asserts that the program being compiled does not perform any floating-point operations. This option is presently supported only by some bare-metal MIPS configurations, where it may select a special set of libraries that lack all floating-point support (including, for example, the floating-point "printf" formats). If code compiled with "-mno-float" accidentally contains floating-point operations, it is likely to suffer a link-time or run-time failure.
-
-msingle-float
-
Assume that the floating-point coprocessor only supports single-precision operations.
-
-mdouble-float
-
Assume that the floating-point coprocessor supports double-precision operations. This is the default.
-
-mllsc
-
-
-mno-llsc
-
Use (do not use) ll, sc, and sync instructions to implement atomic memory built-in functions. When neither option is specified, GCC uses the instructions if the target architecture supports them.
-mllsc is useful if the runtime environment can emulate the instructions and -mno-llsc can be useful when compiling for nonstandard ISAs. You can make either option the default by configuring GCC with --with-llsc and --without-llsc respectively. --with-llsc is the default for some configurations; see the installation documentation for details.
-
-mdsp
-
-
-mno-dsp
-
Use (do not use) revision 1 of the MIPS DSP ASE.
This option defines the preprocessor macro __mips_dsp. It also defines __mips_dsp_rev to 1.
-
-mdspr2
-
-
-mno-dspr2
-
Use (do not use) revision 2 of the MIPS DSP ASE.
This option defines the preprocessor macros __mips_dsp and __mips_dspr2. It also defines __mips_dsp_rev to 2.
-
-msmartmips
-
-
-mno-smartmips
-
Use (do not use) the MIPS SmartMIPS ASE.
-
-mpaired-single
-
-
-mno-paired-single
-
Use (do not use) paired-single floating-point instructions.
This option requires hardware floating-point support to be enabled.
-
-mdmx
-
-
-mno-mdmx
-
Use (do not use) MIPS Digital Media Extension instructions. This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled.
-
-mips3d
-
-
-mno-mips3d
-
Use (do not use) the MIPS-3D ASE. The option -mips3d implies -mpaired-single.
-
-mmt
-
-
-mno-mt
-
Use (do not use) MT Multithreading instructions.
-
-mmcu
-
-
-mno-mcu
-
Use (do not use) the MIPS MCU ASE instructions.
-
-mlong64
-
Force "long" types to be 64 bits wide. See -mlong32 for an explanation of the default and the way that the pointer size is determined.
-
-mlong32
-
Force "long", "int", and pointer types to be 32 bits wide.
The default size of "int"s, "long"s and pointers depends on the ABI. All the supported ABIs use 32-bit "int"s. The n64 ABI uses 64-bit "long"s, as does the 64-bit EABI; the others use 32-bit "long"s. Pointers are the same size as "long"s, or the same size as integer registers, whichever is smaller.
-
-msym32
-
-
-mno-sym32
-
Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is useful in combination with -mabi=64 and -mno-abicalls because it allows GCC to generate shorter and faster references to symbolic addresses.
-
-G num
-
Put definitions of externally-visible data in a small data section if that data is no bigger than num bytes. GCC can then generate more efficient accesses to the data; see -mgpopt for details.
The default -G option depends on the configuration.
-
-mlocal-sdata
-
-
-mno-local-sdata
-
Extend (do not extend) the -G behavior to local data too, such as to static variables in C. -mlocal-sdata is the default for all configurations.
If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with -mno-local-sdata. You might also want to build large libraries with -mno-local-sdata, so that the libraries leave more room for the main program.
-
-mextern-sdata
-
-
-mno-extern-sdata
-
Assume (do not assume) that externally-defined data is in a small data section if the size of that data is within the -G limit. -mextern-sdata is the default for all configurations.
If you compile a module Mod with -mextern-sdata -G num -mgpopt, and Mod references a variable Var that is no bigger than num bytes, you must make sure that Var is placed in a small data section. If Var is defined by another module, you must either compile that module with a high-enough -G setting or attach a "section" attribute to Var's definition. If Var is common, you must link the application with a high-enough -G setting.
The easiest way of satisfying these restrictions is to compile and link every module with the same -G option. However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported -G setting and additionally using -mno-extern-sdata to stop the library from making assumptions about externally-defined data.
-
-mgpopt
-
-
-mno-gpopt
-
Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see -G, -mlocal-sdata and -mextern-sdata. -mgpopt is the default for all configurations.
-mno-gpopt is useful for cases where the $gp register might not hold the value of "_gp". For example, if the code is part of a library that might be used in a boot monitor, programs that call boot monitor routines pass an unknown value in $gp. (In such situations, the boot monitor itself is usually compiled with -G0.)
-mno-gpopt implies -mno-local-sdata and -mno-extern-sdata.
-
-membedded-data
-
-
-mno-embedded-data
-
Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems.
-
-muninit-const-in-rodata
-
-
-mno-uninit-const-in-rodata
-
Put uninitialized "const" variables in the read-only data section. This option is only meaningful in conjunction with -membedded-data.
-
-mcode-readable=setting
-
Specify whether GCC may generate code that reads from executable sections. There are three possible settings:
-
-mcode-readable=yes
-
Instructions may freely access executable sections. This is the default setting.
-
-mcode-readable=pcrel
-
MIPS16 PC-relative load instructions can access executable sections, but other instructions must not do so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dual instruction/data SRAM interface and that, like the M4K, automatically redirect PC-relative loads to the instruction RAM.
-
-mcode-readable=no
-
Instructions must not access executable sections. This option can be useful on targets that are configured to have a dual instruction/data SRAM interface but that (unlike the M4K) do not automatically redirect PC-relative loads to the instruction RAM.
-
-msplit-addresses
-
-
-mno-split-addresses
-
Enable (disable) use of the "%hi()" and "%lo()" assembler relocation operators. This option has been superseded by -mexplicit-relocs but is retained for backwards compatibility.
-
-mexplicit-relocs
-
-
-mno-explicit-relocs
-
Use (do not use) assembler relocation operators when dealing with symbolic addresses. The alternative, selected by -mno-explicit-relocs, is to use assembler macros instead.
-mexplicit-relocs is the default if GCC was configured to use an assembler that supports relocation operators.
-
-mcheck-zero-division
-
-
-mno-check-zero-division
-
Trap (do not trap) on integer division by zero.
The default is -mcheck-zero-division.
-
-mdivide-traps
-
-
-mdivide-breaks
-
MIPS systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal ("SIGFPE"). Use -mdivide-traps to allow conditional traps on architectures that support them and -mdivide-breaks to force the use of breaks.
The default is usually -mdivide-traps, but this can be overridden at configure time using --with-divide=breaks. Divide-by-zero checks can be completely disabled using -mno-check-zero-division.
-
-mmemcpy
-
-
-mno-memcpy
-
Force (do not force) the use of "memcpy()" for non-trivial block moves. The default is -mno-memcpy, which allows GCC to inline most constant-sized copies.
-
-mlong-calls
-
-
-mno-long-calls
-
Disable (do not disable) use of the "jal" instruction. Calling functions using "jal" is more efficient but requires the caller and callee to be in the same 256 megabyte segment.
This option has no effect on abicalls code. The default is -mno-long-calls.
-
-mmad
-
-
-mno-mad
-
Enable (disable) use of the "mad", "madu" and "mul" instructions, as provided by the R4650 ISA.
-
-mfused-madd
-
-
-mno-fused-madd
-
Enable (disable) use of the floating-point multiply-accumulate instructions, when they are available. The default is -mfused-madd.
On the R8000 CPU when multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances. On other processors the result is numerically identical to the equivalent computation using separate multiply, add, subtract and negate instructions.
-
-nocpp
-
Tell the MIPS assembler to not run its preprocessor over user assembler files (with a .s suffix) when assembling them.
-
-mfix-24k
-
-
-mno-fix-24k
-
Work around the 24K E48 (lost data on stores during refill) errata. The workarounds are implemented by the assembler rather than by GCC.
-
-mfix-r4000
-
-
-mno-fix-r4000
-
Work around certain R4000 CPU errata:
-
-
-
A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division.
-
-
-
A double-word or a variable shift may give an incorrect result if executed while an integer multiplication is in progress.
-
-
-
An integer division may give an incorrect result if started in a delay slot of a taken branch or a jump.
-
-mfix-r4400
-
-
-mno-fix-r4400
-
Work around certain R4400 CPU errata:
-
-
-
A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division.
-
-mfix-r10000
-
-
-mno-fix-r10000
-
Work around certain R10000 errata:
-
-
-
"ll"/"sc" sequences may not behave atomically on revisions prior to 3.0. They may deadlock on revisions 2.6 and earlier.
This option can only be used if the target architecture supports branch-likely instructions.
-mfix-r10000 is the default when
-march=r10000 is used;
-mno-fix-r10000 is the default otherwise.
-
-mfix-vr4120
-
-
-mno-fix-vr4120
-
Work around certain VR4120 errata:
-
-
-
"dmultu" does not always produce the correct result.
-
-
-
"div" and "ddiv" do not always produce the correct result if one of the operands is negative.
The workarounds for the division errata rely on special functions in
libgcc.a. At present, these functions are only provided by the "mips64vr*-elf" configurations.
Other VR4120 errata require a NOP to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself.
-
-mfix-vr4130
-
Work around the VR4130 "mflo"/"mfhi" errata. The workarounds are implemented by the assembler rather than by GCC, although GCC avoids using "mflo" and "mfhi" if the VR4130 "macc", "macchi", "dmacc" and "dmacchi" instructions are available instead.
-
-mfix-sb1
-
-
-mno-fix-sb1
-
Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 "F1" and "F2" floating-point errata.)
-
-mr10k-cache-barrier=setting
-
Specify whether GCC should insert cache barriers to avoid the side-effects of speculation on R10K processors.
In common with many processors, the R10K tries to predict the outcome of a conditional branch and speculatively executes instructions from the "taken" branch. It later aborts these instructions if the predicted outcome is wrong. However, on the R10K, even aborted instructions can have side effects.
This problem only affects kernel stores and, depending on the system, kernel loads. As an example, a speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even if the store itself is later aborted. If a DMA operation writes to the same area of memory before the "dirty" line is flushed, the cached data overwrites the DMA-ed data. See the R10K processor manual for a full description, including other potential problems.
One workaround is to insert cache barrier instructions before every memory access that might be speculatively executed and that might have side effects even if aborted. -mr10k-cache-barrier=setting controls GCC's implementation of this workaround. It assumes that aborted accesses to any byte in the following regions does not have side effects:
-
1.
-
the memory occupied by the current function's stack frame;
-
2.
-
the memory occupied by an incoming stack argument;
-
3.
-
the memory occupied by an object with a link-time-constant address.
It is the kernel's responsibility to ensure that speculative accesses to these regions are indeed safe.
If the input program contains a function declaration such as:
void foo (void);
then the implementation of "foo" must allow "j foo" and "jal foo" to be executed speculatively. GCC honors this restriction for functions it compiles itself. It expects non-GCC functions (such as hand-written assembly code) to do the same.
The option has three forms:
-
-mr10k-cache-barrier=load-store
-
Insert a cache barrier before a load or store that might be speculatively executed and that might have side effects even if aborted.
-
-mr10k-cache-barrier=store
-
Insert a cache barrier before a store that might be speculatively executed and that might have side effects even if aborted.
-
-mr10k-cache-barrier=none
-
Disable the insertion of cache barriers. This is the default setting.
-
-mflush-func=func
-
-
-mno-flush-func
-
Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same arguments as the common "_flush_func()", that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either _flush_func or __cpu_flush.
-
mbranch-cost=num
-
Set the cost of branches to roughly num "simple" instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. A zero cost redundantly selects the default, which is based on the -mtune setting.
-
-mbranch-likely
-
-
-mno-branch-likely
-
Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors that implement those architectures; for those, Branch Likely instructions are not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use.
-
-mfp-exceptions
-
-
-mno-fp-exceptions
-
Specifies whether FP exceptions are enabled. This affects how FP instructions are scheduled for some processors. The default is that FP exceptions are enabled.
For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe.
-
-mvr4130-align
-
-
-mno-vr4130-align
-
The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned. When this option is enabled, GCC aligns pairs of instructions that it thinks should execute in parallel.
This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level -O3.
-
-msynci
-
-
-mno-synci
-
Enable (disable) generation of "synci" instructions on architectures that support it. The "synci" instructions (if enabled) are generated when "__builtin___clear_cache()" is compiled.
This option defaults to "-mno-synci", but the default can be overridden by configuring with "--with-synci".
When compiling code for single processor systems, it is generally safe to use "synci". However, on many multi-core (SMP) systems, it does not invalidate the instruction caches on all cores and may lead to undefined behavior.
-
-mrelax-pic-calls
-
-
-mno-relax-pic-calls
-
Try to turn PIC calls that are normally dispatched via register $25 into direct calls. This is only possible if the linker can resolve the destination at link-time and if the destination is within range for a direct call.
-mrelax-pic-calls is the default if GCC was configured to use an assembler and a linker that support the ".reloc" assembly directive and "-mexplicit-relocs" is in effect. With "-mno-explicit-relocs", this optimization can be performed by the assembler and the linker alone without help from the compiler.
-
-mmcount-ra-address
-
-
-mno-mcount-ra-address
-
Emit (do not emit) code that allows "_mcount" to modify the calling function's return address. When enabled, this option extends the usual "_mcount" interface with a new ra-address parameter, which has type "intptr_t *" and is passed in register $12. "_mcount" can then modify the return address by doing both of the following:
-
•
-
Returning the new address in register $31.
-
•
-
Storing the new address in "*ra-address", if ra-address is nonnull.
The default is
-mno-mcount-ra-address.
MMIX Options
These options are defined for the MMIX:
-
-mlibfuncs
-
-
-mno-libfuncs
-
Specify that intrinsic library functions are being compiled, passing all values in registers, no matter the size.
-
-mepsilon
-
-
-mno-epsilon
-
Generate floating-point comparison instructions that compare with respect to the "rE" epsilon register.
-
-mabi=mmixware
-
-
-mabi=gnu
-
Generate code that passes function parameters and return values that (in the called function) are seen as registers $0 and up, as opposed to the GNU ABI which uses global registers $231 and up.
-
-mzero-extend
-
-
-mno-zero-extend
-
When reading data from memory in sizes shorter than 64 bits, use (do not use) zero-extending load instructions by default, rather than sign-extending ones.
-
-mknuthdiv
-
-
-mno-knuthdiv
-
Make the result of a division yielding a remainder have the same sign as the divisor. With the default, -mno-knuthdiv, the sign of the remainder follows the sign of the dividend. Both methods are arithmetically valid, the latter being almost exclusively used.
-
-mtoplevel-symbols
-
-
-mno-toplevel-symbols
-
Prepend (do not prepend) a : to all global symbols, so the assembly code can be used with the "PREFIX" assembly directive.
-
-melf
-
Generate an executable in the ELF format, rather than the default mmo format used by the mmix simulator.
-
-mbranch-predict
-
-
-mno-branch-predict
-
Use (do not use) the probable-branch instructions, when static branch prediction indicates a probable branch.
-
-mbase-addresses
-
-
-mno-base-addresses
-
Generate (do not generate) code that uses base addresses. Using a base address automatically generates a request (handled by the assembler and the linker) for a constant to be set up in a global register. The register is used for one or more base address requests within the range 0 to 255 from the value held in the register. The generally leads to short and fast code, but the number of different data items that can be addressed is limited. This means that a program that uses lots of static data may require -mno-base-addresses.
-
-msingle-exit
-
-
-mno-single-exit
-
Force (do not force) generated code to have a single exit point in each function.
MN10300 Options
These -m options are defined for Matsushita MN10300 architectures:
-
-mmult-bug
-
Generate code to avoid bugs in the multiply instructions for the MN10300 processors. This is the default.
-
-mno-mult-bug
-
Do not generate code to avoid bugs in the multiply instructions for the MN10300 processors.
-
-mam33
-
Generate code using features specific to the AM33 processor.
-
-mno-am33
-
Do not generate code using features specific to the AM33 processor. This is the default.
-
-mam33-2
-
Generate code using features specific to the AM33/2.0 processor.
-
-mam34
-
Generate code using features specific to the AM34 processor.
-
-mtune=cpu-type
-
Use the timing characteristics of the indicated CPU type when scheduling instructions. This does not change the targeted processor type. The CPU type must be one of mn10300, am33, am33-2 or am34.
-
-mreturn-pointer-on-d0
-
When generating a function that returns a pointer, return the pointer in both "a0" and "d0". Otherwise, the pointer is returned only in "a0", and attempts to call such functions without a prototype result in errors. Note that this option is on by default; use -mno-return-pointer-on-d0 to disable it.
-
-mno-crt0
-
Do not link in the C run-time initialization object file.
-
-mrelax
-
Indicate to the linker that it should perform a relaxation optimization pass to shorten branches, calls and absolute memory addresses. This option only has an effect when used on the command line for the final link step.
This option makes symbolic debugging impossible.
-
-mliw
-
Allow the compiler to generate Long Instruction Word instructions if the target is the AM33 or later. This is the default. This option defines the preprocessor macro __LIW__.
-
-mnoliw
-
Do not allow the compiler to generate Long Instruction Word instructions. This option defines the preprocessor macro __NO_LIW__.
-
-msetlb
-
Allow the compiler to generate the SETLB and Lcc instructions if the target is the AM33 or later. This is the default. This option defines the preprocessor macro __SETLB__.
-
-mnosetlb
-
Do not allow the compiler to generate SETLB or Lcc instructions. This option defines the preprocessor macro __NO_SETLB__.
Moxie Options
-
-meb
-
Generate big-endian code. This is the default for moxie-*-* configurations.
-
-mel
-
Generate little-endian code.
-
-mno-crt0
-
Do not link in the C run-time initialization object file.
PDP-11 Options
These options are defined for the PDP-11:
-
-mfpu
-
Use hardware FPP floating point. This is the default. (FIS floating point on the PDP-11/40 is not supported.)
-
-msoft-float
-
Do not use hardware floating point.
-
-mac0
-
Return floating-point results in ac0 (fr0 in Unix assembler syntax).
-
-mno-ac0
-
Return floating-point results in memory. This is the default.
-
-m40
-
Generate code for a PDP-11/40.
-
-m45
-
Generate code for a PDP-11/45. This is the default.
-
-m10
-
Generate code for a PDP-11/10.
-
-mbcopy-builtin
-
Use inline "movmemhi" patterns for copying memory. This is the default.
-
-mbcopy
-
Do not use inline "movmemhi" patterns for copying memory.
-
-mint16
-
-
-mno-int32
-
Use 16-bit "int". This is the default.
-
-mint32
-
-
-mno-int16
-
Use 32-bit "int".
-
-mfloat64
-
-
-mno-float32
-
Use 64-bit "float". This is the default.
-
-mfloat32
-
-
-mno-float64
-
Use 32-bit "float".
-
-mabshi
-
Use "abshi2" pattern. This is the default.
-
-mno-abshi
-
Do not use "abshi2" pattern.
-
-mbranch-expensive
-
Pretend that branches are expensive. This is for experimenting with code generation only.
-
-mbranch-cheap
-
Do not pretend that branches are expensive. This is the default.
-
-munix-asm
-
Use Unix assembler syntax. This is the default when configured for pdp11-*-bsd.
-
-mdec-asm
-
Use DEC assembler syntax. This is the default when configured for any PDP-11 target other than pdp11-*-bsd.
picoChip Options
These -m options are defined for picoChip implementations:
-
-mae=ae_type
-
Set the instruction set, register set, and instruction scheduling parameters for array element type ae_type. Supported values for ae_type are ANY, MUL, and MAC.
-mae=ANY selects a completely generic AE type. Code generated with this option runs on any of the other AE types. The code is not as efficient as it would be if compiled for a specific AE type, and some types of operation (e.g., multiplication) do not work properly on all types of AE.
-mae=MUL selects a MUL AE type. This is the most useful AE type for compiled code, and is the default.
-mae=MAC selects a DSP-style MAC AE. Code compiled with this option may suffer from poor performance of byte (char) manipulation, since the DSP AE does not provide hardware support for byte load/stores.
-
-msymbol-as-address
-
Enable the compiler to directly use a symbol name as an address in a load/store instruction, without first loading it into a register. Typically, the use of this option generates larger programs, which run faster than when the option isn't used. However, the results vary from program to program, so it is left as a user option, rather than being permanently enabled.
-
-mno-inefficient-warnings
-
Disables warnings about the generation of inefficient code. These warnings can be generated, for example, when compiling code that performs byte-level memory operations on the MAC AE type. The MAC AE has no hardware support for byte-level memory operations, so all byte load/stores must be synthesized from word load/store operations. This is inefficient and a warning is generated to indicate that you should rewrite the code to avoid byte operations, or to target an AE type that has the necessary hardware support. This option disables these warnings.
PowerPC Options
These are listed under
RL78 Options
-
-msim
-
Links in additional target libraries to support operation within a simulator.
-
-mmul=none
-
-
-mmul=g13
-
-
-mmul=rl78
-
Specifies the type of hardware multiplication support to be used. The default is "none", which uses software multiplication functions. The "g13" option is for the hardware multiply/divide peripheral only on the RL78/G13 targets. The "rl78" option is for the standard hardware multiplication defined in the RL78 software manual.
IBM RS/6000 and PowerPC Options
These -m options are defined for the IBM RS/6000 and PowerPC:
-
-mpowerpc-gpopt
-
-
-mno-powerpc-gpopt
-
-
-mpowerpc-gfxopt
-
-
-mno-powerpc-gfxopt
-
-
-mpowerpc64
-
-
-mno-powerpc64
-
-
-mmfcrf
-
-
-mno-mfcrf
-
-
-mpopcntb
-
-
-mno-popcntb
-
-
-mpopcntd
-
-
-mno-popcntd
-
-
-mfprnd
-
-
-mno-fprnd
-
-
-mcmpb
-
-
-mno-cmpb
-
-
-mmfpgpr
-
-
-mno-mfpgpr
-
-
-mhard-dfp
-
-
-mno-hard-dfp
-
You use these options to specify which instructions are available on the processor you are using. The default value of these options is determined when configuring GCC. Specifying the -mcpu=cpu_type overrides the specification of these options. We recommend you use the -mcpu=cpu_type option rather than the options listed above.
Specifying -mpowerpc-gpopt allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. Specifying -mpowerpc-gfxopt allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select.
The -mmfcrf option allows GCC to generate the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture. The -mpopcntb option allows GCC to generate the popcount and double-precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture. The -mpopcntd option allows GCC to generate the popcount instruction implemented on the POWER7 processor and other processors that support the PowerPC V2.06 architecture. The -mfprnd option allows GCC to generate the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. The -mcmpb option allows GCC to generate the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture. The -mmfpgpr option allows GCC to generate the FP move to/from general-purpose register instructions implemented on the POWER6X processor and other processors that support the extended PowerPC V2.05 architecture. The -mhard-dfp option allows GCC to generate the decimal floating-point instructions implemented on some POWER processors.
The -mpowerpc64 option allows GCC to generate the additional 64-bit instructions that are found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to -mno-powerpc64.
-
-mcpu=cpu_type
-
Set architecture type, register usage, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are 401, 403, 405, 405fp, 440, 440fp, 464, 464fp, 476, 476fp, 505, 601, 602, 603, 603e, 604, 604e, 620, 630, 740, 7400, 7450, 750, 801, 821, 823, 860, 970, 8540, a2, e300c2, e300c3, e500mc, e500mc64, e5500, e6500, ec603e, G3, G4, G5, titan, power3, power4, power5, power5+, power6, power6x, power7, power8, powerpc, powerpc64, and rs64.
-mcpu=powerpc, and -mcpu=powerpc64 specify pure 32-bit PowerPC and 64-bit PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes.
The other options specify a specific processor. Code generated under those options runs best on that processor, and may not run at all on others.
The -mcpu options automatically enable or disable the following options:
-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple -mpopcntb -mpopcntd -mpowerpc64 -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx
The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn't necessarily reflect the actual hardware's capabilities. If you wish to set an individual option to a particular value, you may specify it after the -mcpu option, like -mcpu=970 -mno-altivec.
On AIX, the -maltivec and -mpowerpc64 options are not enabled or disabled by the -mcpu option at present because AIX does not have full support for these options. You may still enable or disable them individually if you're sure it'll work in your environment.
-
-mtune=cpu_type
-
Set the instruction scheduling parameters for machine type cpu_type, but do not set the architecture type or register usage, as -mcpu=cpu_type does. The same values for cpu_type are used for -mtune as for -mcpu. If both are specified, the code generated uses the architecture and registers set by -mcpu, but the scheduling parameters set by -mtune.
-
-mcmodel=small
-
Generate PowerPC64 code for the small model: The TOC is limited to 64k.
-
-mcmodel=medium
-
Generate PowerPC64 code for the medium model: The TOC and other static data may be up to a total of 4G in size.
-
-mcmodel=large
-
Generate PowerPC64 code for the large model: The TOC may be up to 4G in size. Other data and code is only limited by the 64-bit address space.
-
-maltivec
-
-
-mno-altivec
-
Generate code that uses (does not use) AltiVec instructions, and also enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set -mabi=altivec to adjust the current ABI with AltiVec ABI enhancements.
-
-mvrsave
-
-
-mno-vrsave
-
Generate VRSAVE instructions when generating AltiVec code.
-
-mgen-cell-microcode
-
Generate Cell microcode instructions.
-
-mwarn-cell-microcode
-
Warn when a Cell microcode instruction is emitted. An example of a Cell microcode instruction is a variable shift.
-
-msecure-plt
-
Generate code that allows ld and ld.so to build executables and shared libraries with non-executable ".plt" and ".got" sections. This is a PowerPC 32-bit SYSV ABI option.
-
-mbss-plt
-
Generate code that uses a BSS ".plt" section that ld.so fills in, and requires ".plt" and ".got" sections that are both writable and executable. This is a PowerPC 32-bit SYSV ABI option.
-
-misel
-
-
-mno-isel
-
This switch enables or disables the generation of ISEL instructions.
-
-misel=yes/no
-
This switch has been deprecated. Use -misel and -mno-isel instead.
-
-mspe
-
-
-mno-spe
-
This switch enables or disables the generation of SPE simd instructions.
-
-mpaired
-
-
-mno-paired
-
This switch enables or disables the generation of PAIRED simd instructions.
-
-mspe=yes/no
-
This option has been deprecated. Use -mspe and -mno-spe instead.
-
-mvsx
-
-
-mno-vsx
-
Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set.
-
-mfloat-gprs=yes/single/double/no
-
-
-mfloat-gprs
-
This switch enables or disables the generation of floating-point operations on the general-purpose registers for architectures that support it.
The argument yes or single enables the use of single-precision floating-point operations.
The argument double enables the use of single and double-precision floating-point operations.
The argument no disables floating-point operations on the general-purpose registers.
This option is currently only available on the MPC854x.
-
-m32
-
-
-m64
-
Generate code for 32-bit or 64-bit environments of Darwin and SVR4 targets (including GNU/Linux). The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any PowerPC variant. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits, and generates code for PowerPC64, as for -mpowerpc64.
-
-mfull-toc
-
-
-mno-fp-in-toc
-
-
-mno-sum-in-toc
-
-
-mminimal-toc
-
Modify generation of the TOC (Table Of Contents), which is created for every executable file. The -mfull-toc option is selected by default. In that case, GCC allocates at least one TOC entry for each unique non-automatic variable reference in your program. GCC also places floating-point constants in the TOC. However, only 16,384 entries are available in the TOC.
If you receive a linker error message that saying you have overflowed the available TOC space, you can reduce the amount of TOC space used with the -mno-fp-in-toc and -mno-sum-in-toc options. -mno-fp-in-toc prevents GCC from putting floating-point constants in the TOC and -mno-sum-in-toc forces GCC to generate code to calculate the sum of an address and a constant at run time instead of putting that sum into the TOC. You may specify one or both of these options. Each causes GCC to produce very slightly slower and larger code at the expense of conserving TOC space.
If you still run out of space in the TOC even when you specify both of these options, specify -mminimal-toc instead. This option causes GCC to make only one TOC entry for every file. When you specify this option, GCC produces code that is slower and larger but which uses extremely little TOC space. You may wish to use this option only on files that contain less frequently-executed code.
-
-maix64
-
-
-maix32
-
Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit "long" type, and the infrastructure needed to support them. Specifying -maix64 implies -mpowerpc64, while -maix32 disables the 64-bit ABI and implies -mno-powerpc64. GCC defaults to -maix32.
-
-mxl-compat
-
-
-mno-xl-compat
-
Produce code that conforms more closely to IBM XL compiler semantics when using AIX-compatible ABI. Pass floating-point arguments to prototyped functions beyond the register save area (RSA) on the stack in addition to argument FPRs. Do not assume that most significant double in 128-bit long double value is properly rounded when comparing values and converting to double. Use XL symbol names for long double support routines.
The AIX calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the address of its arguments with fewer arguments than declared. IBM XL compilers access floating-point arguments that do not fit in the RSA from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization.
-
-mpe
-
Support IBM RS/6000 SP Parallel Environment (PE). Link an application written to use message passing with special startup code to enable the application to run. The system must have PE installed in the standard location ( /usr/lpp/ppe.poe/), or the specs file must be overridden with the -specs= option to specify the appropriate directory location. The Parallel Environment does not support threads, so the -mpe option and the -pthread option are incompatible.
-
-malign-natural
-
-
-malign-power
-
On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option -malign-natural overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option -malign-power instructs GCC to follow the ABI-specified alignment rules. GCC defaults to the standard alignment defined in the ABI.
On 64-bit Darwin, natural alignment is the default, and -malign-power is not supported.
-
-msoft-float
-
-
-mhard-float
-
Generate code that does not use (uses) the floating-point register set. Software floating-point emulation is provided if you use the -msoft-float option, and pass the option to GCC when linking.
-
-msingle-float
-
-
-mdouble-float
-
Generate code for single- or double-precision floating-point operations. -mdouble-float implies -msingle-float.
-
-msimple-fpu
-
Do not generate "sqrt" and "div" instructions for hardware floating-point unit.
-
-mfpu=name
-
Specify type of floating-point unit. Valid values for name are sp_lite (equivalent to -msingle-float -msimple-fpu), dp_lite (equivalent to -mdouble-float -msimple-fpu), sp_full (equivalent to -msingle-float), and dp_full (equivalent to -mdouble-float).
-
-mxilinx-fpu
-
Perform optimizations for the floating-point unit on Xilinx PPC 405/440.
-
-mmultiple
-
-
-mno-multiple
-
Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use -mmultiple on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode.
-
-mstring
-
-
-mno-string
-
Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use -mstring on little-endian PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode.
-
-mupdate
-
-
-mno-update
-
Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location. These instructions are generated by default. If you use -mno-update, there is a small window between the time that the stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data.
-
-mavoid-indexed-addresses
-
-
-mno-avoid-indexed-addresses
-
Generate code that tries to avoid (not avoid) the use of indexed load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option is enabled by default when targeting Power6 and disabled otherwise.
-
-mfused-madd
-
-
-mno-fused-madd
-
Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used. The machine-dependent -mfused-madd option is now mapped to the machine-independent -ffp-contract=fast option, and -mno-fused-madd is mapped to -ffp-contract=off.
-
-mmulhw
-
-
-mno-mulhw
-
Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targeting those processors.
-
-mdlmzb
-
-
-mno-dlmzb
-
Generate code that uses (does not use) the string-search dlmzb instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targeting those processors.
-
-mno-bit-align
-
-
-mbit-align
-
On System V.4 and embedded PowerPC systems do not (do) force structures and unions that contain bit-fields to be aligned to the base type of the bit-field.
For example, by default a structure containing nothing but 8 "unsigned" bit-fields of length 1 is aligned to a 4-byte boundary and has a size of 4 bytes. By using -mno-bit-align, the structure is aligned to a 1-byte boundary and is 1 byte in size.
-
-mno-strict-align
-
-
-mstrict-align
-
On System V.4 and embedded PowerPC systems do not (do) assume that unaligned memory references are handled by the system.
-
-mrelocatable
-
-
-mno-relocatable
-
Generate code that allows (does not allow) a static executable to be relocated to a different address at run time. A simple embedded PowerPC system loader should relocate the entire contents of ".got2" and 4-byte locations listed in the ".fixup" section, a table of 32-bit addresses generated by this option. For this to work, all objects linked together must be compiled with -mrelocatable or -mrelocatable-lib. -mrelocatable code aligns the stack to an 8-byte boundary.
-
-mrelocatable-lib
-
-
-mno-relocatable-lib
-
Like -mrelocatable, -mrelocatable-lib generates a ".fixup" section to allow static executables to be relocated at run time, but -mrelocatable-lib does not use the smaller stack alignment of -mrelocatable. Objects compiled with -mrelocatable-lib may be linked with objects compiled with any combination of the -mrelocatable options.
-
-mno-toc
-
-
-mtoc
-
On System V.4 and embedded PowerPC systems do not (do) assume that register 2 contains a pointer to a global area pointing to the addresses used in the program.
-
-mlittle
-
-
-mlittle-endian
-
On System V.4 and embedded PowerPC systems compile code for the processor in little-endian mode. The -mlittle-endian option is the same as -mlittle.
-
-mbig
-
-
-mbig-endian
-
On System V.4 and embedded PowerPC systems compile code for the processor in big-endian mode. The -mbig-endian option is the same as -mbig.
-
-mdynamic-no-pic
-
On Darwin and Mac OS X systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries.
-
-msingle-pic-base
-
Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins.
-
-mprioritize-restricted-insns=priority
-
This option controls the priority that is assigned to dispatch-slot restricted instructions during the second scheduling pass. The argument priority takes the value 0, 1, or 2 to assign no, highest, or second-highest (respectively) priority to dispatch-slot restricted instructions.
-
-msched-costly-dep=dependence_type
-
This option controls which dependences are considered costly by the target during instruction scheduling. The argument dependence_type takes one of the following values:
-
no
-
No dependence is costly.
-
all
-
All dependences are costly.
-
true_store_to_load
-
A true dependence from store to load is costly.
-
store_to_load
-
Any dependence from store to load is costly.
-
number
-
Any dependence for which the latency is greater than or equal to number is costly.
-
-minsert-sched-nops=scheme
-
This option controls which NOP insertion scheme is used during the second scheduling pass. The argument scheme takes one of the following values:
-
no
-
Don't insert NOPs.
-
pad
-
Pad with NOPs any dispatch group that has vacant issue slots, according to the scheduler's grouping.
-
regroup_exact
-
Insert NOPs to force costly dependent insns into separate groups. Insert exactly as many NOPs as needed to force an insn to a new group, according to the estimated processor grouping.
-
number
-
Insert NOPs to force costly dependent insns into separate groups. Insert number NOPs to force an insn to a new group.
-
-mcall-sysv
-
On System V.4 and embedded PowerPC systems compile code using calling conventions that adhere to the March 1995 draft of the System V Application Binary Interface, PowerPC processor supplement. This is the default unless you configured GCC using powerpc-*-eabiaix.
-
-mcall-sysv-eabi
-
-
-mcall-eabi
-
Specify both -mcall-sysv and -meabi options.
-
-mcall-sysv-noeabi
-
Specify both -mcall-sysv and -mno-eabi options.
-
-mcall-aixdesc
-
On System V.4 and embedded PowerPC systems compile code for the AIX operating system.
-
-mcall-linux
-
On System V.4 and embedded PowerPC systems compile code for the Linux-based GNU system.
-
-mcall-freebsd
-
On System V.4 and embedded PowerPC systems compile code for the FreeBSD operating system.
-
-mcall-netbsd
-
On System V.4 and embedded PowerPC systems compile code for the NetBSD operating system.
-
-mcall-openbsd
-
On System V.4 and embedded PowerPC systems compile code for the OpenBSD operating system.
-
-maix-struct-return
-
Return all structures in memory (as specified by the AIX ABI).
-
-msvr4-struct-return
-
Return structures smaller than 8 bytes in registers (as specified by the SVR4 ABI).
-
-mabi=abi-type
-
Extend the current ABI with a particular extension, or remove such extension. Valid values are altivec, no-altivec, spe, no-spe, ibmlongdouble, ieeelongdouble.
-
-mabi=spe
-
Extend the current ABI with SPE ABI extensions. This does not change the default ABI, instead it adds the SPE ABI extensions to the current ABI.
-
-mabi=no-spe
-
Disable Book-E SPE ABI extensions for the current ABI.
-
-mabi=ibmlongdouble
-
Change the current ABI to use IBM extended-precision long double. This is a PowerPC 32-bit SYSV ABI option.
-
-mabi=ieeelongdouble
-
Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option.
-
-mprototype
-
-
-mno-prototype
-
On System V.4 and embedded PowerPC systems assume that all calls to variable argument functions are properly prototyped. Otherwise, the compiler must insert an instruction before every non-prototyped call to set or clear bit 6 of the condition code register ( CR) to indicate whether floating-point values are passed in the floating-point registers in case the function takes variable arguments. With -mprototype, only calls to prototyped variable argument functions set or clear the bit.
-
-msim
-
On embedded PowerPC systems, assume that the startup module is called sim-crt0.o and that the standard C libraries are libsim.a and libc.a. This is the default for powerpc-*-eabisim configurations.
-
-mmvme
-
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libmvme.a and libc.a.
-
-mads
-
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libads.a and libc.a.
-
-myellowknife
-
On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libyk.a and libc.a.
-
-mvxworks
-
On System V.4 and embedded PowerPC systems, specify that you are compiling for a VxWorks system.
-
-memb
-
On embedded PowerPC systems, set the PPC_EMB bit in the ELF flags header to indicate that eabi extended relocations are used.
-
-meabi
-
-
-mno-eabi
-
On System V.4 and embedded PowerPC systems do (do not) adhere to the Embedded Applications Binary Interface (EABI), which is a set of modifications to the System V.4 specifications. Selecting -meabi means that the stack is aligned to an 8-byte boundary, a function "__eabi" is called from "main" to set up the EABI environment, and the -msdata option can use both "r2" and "r13" to point to two separate small data areas. Selecting -mno-eabi means that the stack is aligned to a 16-byte boundary, no EABI initialization function is called from "main", and the -msdata option only uses "r13" to point to a single small data area. The -meabi option is on by default if you configured GCC using one of the powerpc*-*-eabi* options.
-
-msdata=eabi
-
On System V.4 and embedded PowerPC systems, put small initialized "const" global and static data in the .sdata2 section, which is pointed to by register "r2". Put small initialized non-"const" global and static data in the .sdata section, which is pointed to by register "r13". Put small uninitialized global and static data in the .sbss section, which is adjacent to the .sdata section. The -msdata=eabi option is incompatible with the -mrelocatable option. The -msdata=eabi option also sets the -memb option.
-
-msdata=sysv
-
On System V.4 and embedded PowerPC systems, put small global and static data in the .sdata section, which is pointed to by register "r13". Put small uninitialized global and static data in the .sbss section, which is adjacent to the .sdata section. The -msdata=sysv option is incompatible with the -mrelocatable option.
-
-msdata=default
-
-
-msdata
-
On System V.4 and embedded PowerPC systems, if -meabi is used, compile code the same as -msdata=eabi, otherwise compile code the same as -msdata=sysv.
-
-msdata=data
-
On System V.4 and embedded PowerPC systems, put small global data in the .sdata section. Put small uninitialized global data in the .sbss section. Do not use register "r13" to address small data however. This is the default behavior unless other -msdata options are used.
-
-msdata=none
-
-
-mno-sdata
-
On embedded PowerPC systems, put all initialized global and static data in the .data section, and all uninitialized data in the .bss section.
-
-mblock-move-inline-limit=num
-
Inline all block moves (such as calls to "memcpy" or structure copies) less than or equal to num bytes. The minimum value for num is 32 bytes on 32-bit targets and 64 bytes on 64-bit targets. The default value is target-specific.
-
-G num
-
On embedded PowerPC systems, put global and static items less than or equal to num bytes into the small data or BSS sections instead of the normal data or BSS section. By default, num is 8. The -G num switch is also passed to the linker. All modules should be compiled with the same -G num value.
-
-mregnames
-
-
-mno-regnames
-
On System V.4 and embedded PowerPC systems do (do not) emit register names in the assembly language output using symbolic forms.
-
-mlongcall
-
-
-mno-longcall
-
By default assume that all calls are far away so that a longer and more expensive calling sequence is required. This is required for calls farther than 32 megabytes (33,554,432 bytes) from the current location. A short call is generated if the compiler knows the call cannot be that far away. This setting can be overridden by the "shortcall" function attribute, or by "#pragma longcall(0)".
Some linkers are capable of detecting out-of-range calls and generating glue code on the fly. On these systems, long calls are unnecessary and generate slower code. As of this writing, the AIX linker can do this, as can the GNU linker for PowerPC/64. It is planned to add this feature to the GNU linker for 32-bit PowerPC systems as well.
On Darwin/PPC systems, "#pragma longcall" generates "jbsr callee, L42", plus a branch island (glue code). The two target addresses represent the callee and the branch island. The Darwin/PPC linker prefers the first address and generates a "bl callee" if the PPC "bl" instruction reaches the callee directly; otherwise, the linker generates "bl L42" to call the branch island. The branch island is appended to the body of the calling function; it computes the full 32-bit address of the callee and jumps to it.
On Mach-O (Darwin) systems, this option directs the compiler emit to the glue for every direct call, and the Darwin linker decides whether to use or discard it.
In the future, GCC may ignore all longcall specifications when the linker is known to generate glue.
-
-mtls-markers
-
-
-mno-tls-markers
-
Mark (do not mark) calls to "__tls_get_addr" with a relocation specifying the function argument. The relocation allows the linker to reliably associate function call with argument setup instructions for TLS optimization, which in turn allows GCC to better schedule the sequence.
-
-pthread
-
Adds support for multithreading with the pthreads library. This option sets flags for both the preprocessor and linker.
-
-mrecip
-
-
-mno-recip
-
This option enables use of the reciprocal estimate and reciprocal square root estimate instructions with additional Newton-Raphson steps to increase precision instead of doing a divide or square root and divide for floating-point arguments. You should use the -ffast-math option when using -mrecip (or at least -funsafe-math-optimizations, -finite-math-only, -freciprocal-math and -fno-trapping-math). Note that while the throughput of the sequence is generally higher than the throughput of the non-reciprocal instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square roots.
-
-mrecip=opt
-
This option controls which reciprocal estimate instructions may be used. opt is a comma-separated list of options, which may be preceded by a "!" to invert the option: "all": enable all estimate instructions, "default": enable the default instructions, equivalent to -mrecip, "none": disable all estimate instructions, equivalent to -mno-recip; "div": enable the reciprocal approximation instructions for both single and double precision; "divf": enable the single-precision reciprocal approximation instructions; "divd": enable the double-precision reciprocal approximation instructions; "rsqrt": enable the reciprocal square root approximation instructions for both single and double precision; "rsqrtf": enable the single-precision reciprocal square root approximation instructions; "rsqrtd": enable the double-precision reciprocal square root approximation instructions;
So, for example, -mrecip=all,!rsqrtd enables all of the reciprocal estimate instructions, except for the "FRSQRTE", "XSRSQRTEDP", and "XVRSQRTEDP" instructions which handle the double-precision reciprocal square root calculations.
-
-mrecip-precision
-
-
-mno-recip-precision
-
Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI. Selecting -mcpu=power6, -mcpu=power7 or -mcpu=power8 automatically selects -mrecip-precision. The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an estimate that converges after three steps.
-
-mveclibabi=type
-
Specifies the ABI type to use for vectorizing intrinsics using an external library. The only type supported at present is "mass", which specifies to use IBM's Mathematical Acceleration Subsystem (MASS) libraries for vectorizing intrinsics using external libraries. GCC currently emits calls to "acosd2", "acosf4", "acoshd2", "acoshf4", "asind2", "asinf4", "asinhd2", "asinhf4", "atan2d2", "atan2f4", "atand2", "atanf4", "atanhd2", "atanhf4", "cbrtd2", "cbrtf4", "cosd2", "cosf4", "coshd2", "coshf4", "erfcd2", "erfcf4", "erfd2", "erff4", "exp2d2", "exp2f4", "expd2", "expf4", "expm1d2", "expm1f4", "hypotd2", "hypotf4", "lgammad2", "lgammaf4", "log10d2", "log10f4", "log1pd2", "log1pf4", "log2d2", "log2f4", "logd2", "logf4", "powd2", "powf4", "sind2", "sinf4", "sinhd2", "sinhf4", "sqrtd2", "sqrtf4", "tand2", "tanf4", "tanhd2", and "tanhf4" when generating code for power7. Both -ftree-vectorize and -funsafe-math-optimizations must also be enabled. The MASS libraries must be specified at link time.
-
-mfriz
-
-
-mno-friz
-
Generate (do not generate) the "friz" instruction when the -funsafe-math-optimizations option is used to optimize rounding of floating-point values to 64-bit integer and back to floating point. The "friz" instruction does not return the same value if the floating-point number is too large to fit in an integer.
-
-mpointers-to-nested-functions
-
-
-mno-pointers-to-nested-functions
-
Generate (do not generate) code to load up the static chain register ( r11) when calling through a pointer on AIX and 64-bit Linux systems where a function pointer points to a 3-word descriptor giving the function address, TOC value to be loaded in register r2, and static chain value to be loaded in register r11. The -mpointers-to-nested-functions is on by default. You cannot call through pointers to nested functions or pointers to functions compiled in other languages that use the static chain if you use the -mno-pointers-to-nested-functions.
-
-msave-toc-indirect
-
-
-mno-save-toc-indirect
-
Generate (do not generate) code to save the TOC value in the reserved stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the pointer. The -mno-save-toc-indirect option is the default.
RX Options
These command-line options are defined for RX targets:
-
-m64bit-doubles
-
-
-m32bit-doubles
-
Make the "double" data type be 64 bits (-m64bit-doubles) or 32 bits ( -m32bit-doubles) in size. The default is -m32bit-doubles. Note RX floating-point hardware only works on 32-bit values, which is why the default is -m32bit-doubles.
-
-fpu
-
-
-nofpu
-
Enables (-fpu) or disables (-nofpu) the use of RX floating-point hardware. The default is enabled for the RX600 series and disabled for the RX200 series.
Floating-point instructions are only generated for 32-bit floating-point values, however, so the FPU hardware is not used for doubles if the -m64bit-doubles option is used.
Note If the -fpu option is enabled then -funsafe-math-optimizations is also enabled automatically. This is because the RX FPU instructions are themselves unsafe.
-
-mcpu=name
-
Selects the type of RX CPU to be targeted. Currently three types are supported, the generic RX600 and RX200 series hardware and the specific RX610 CPU. The default is RX600.
The only difference between RX600 and RX610 is that the RX610 does not support the "MVTIPL" instruction.
The RX200 series does not have a hardware floating-point unit and so -nofpu is enabled by default when this type is selected.
-
-mbig-endian-data
-
-
-mlittle-endian-data
-
Store data (but not code) in the big-endian format. The default is -mlittle-endian-data, i.e. to store data in the little-endian format.
-
-msmall-data-limit=N
-
Specifies the maximum size in bytes of global and static variables which can be placed into the small data area. Using the small data area can lead to smaller and faster code, but the size of area is limited and it is up to the programmer to ensure that the area does not overflow. Also when the small data area is used one of the RX's registers (usually "r13") is reserved for use pointing to this area, so it is no longer available for use by the compiler. This could result in slower and/or larger code if variables are pushed onto the stack instead of being held in this register.
Note, common variables (variables that have not been initialized) and constants are not placed into the small data area as they are assigned to other sections in the output executable.
The default value is zero, which disables this feature. Note, this feature is not enabled by default with higher optimization levels ( -O2 etc) because of the potentially detrimental effects of reserving a register. It is up to the programmer to experiment and discover whether this feature is of benefit to their program. See the description of the -mpid option for a description of how the actual register to hold the small data area pointer is chosen.
-
-msim
-
-
-mno-sim
-
Use the simulator runtime. The default is to use the libgloss board-specific runtime.
-
-mas100-syntax
-
-
-mno-as100-syntax
-
When generating assembler output use a syntax that is compatible with Renesas's AS100 assembler. This syntax can also be handled by the GAS assembler, but it has some restrictions so it is not generated by default.
-
-mmax-constant-size=N
-
Specifies the maximum size, in bytes, of a constant that can be used as an operand in a RX instruction. Although the RX instruction set does allow constants of up to 4 bytes in length to be used in instructions, a longer value equates to a longer instruction. Thus in some circumstances it can be beneficial to restrict the size of constants that are used in instructions. Constants that are too big are instead placed into a constant pool and referenced via register indirection.
The value N can be between 0 and 4. A value of 0 (the default) or 4 means that constants of any size are allowed.
-
-mrelax
-
Enable linker relaxation. Linker relaxation is a process whereby the linker attempts to reduce the size of a program by finding shorter versions of various instructions. Disabled by default.
-
-mint-register=N
-
Specify the number of registers to reserve for fast interrupt handler functions. The value N can be between 0 and 4. A value of 1 means that register "r13" is reserved for the exclusive use of fast interrupt handlers. A value of 2 reserves "r13" and "r12". A value of 3 reserves "r13", "r12" and "r11", and a value of 4 reserves "r13" through "r10". A value of 0, the default, does not reserve any registers.
-
-msave-acc-in-interrupts
-
Specifies that interrupt handler functions should preserve the accumulator register. This is only necessary if normal code might use the accumulator register, for example because it performs 64-bit multiplications. The default is to ignore the accumulator as this makes the interrupt handlers faster.
-
-mpid
-
-
-mno-pid
-
Enables the generation of position independent data. When enabled any access to constant data is done via an offset from a base address held in a register. This allows the location of constant data to be determined at run time without requiring the executable to be relocated, which is a benefit to embedded applications with tight memory constraints. Data that can be modified is not affected by this option.
Note, using this feature reserves a register, usually "r13", for the constant data base address. This can result in slower and/or larger code, especially in complicated functions.
The actual register chosen to hold the constant data base address depends upon whether the -msmall-data-limit and/or the -mint-register command-line options are enabled. Starting with register "r13" and proceeding downwards, registers are allocated first to satisfy the requirements of -mint-register, then -mpid and finally -msmall-data-limit. Thus it is possible for the small data area register to be "r8" if both -mint-register=4 and -mpid are specified on the command line.
By default this feature is not enabled. The default can be restored via the -mno-pid command-line option.
-
-mno-warn-multiple-fast-interrupts
-
-
-mwarn-multiple-fast-interrupts
-
Prevents GCC from issuing a warning message if it finds more than one fast interrupt handler when it is compiling a file. The default is to issue a warning for each extra fast interrupt handler found, as the RX only supports one such interrupt.
Note: The generic GCC command-line option -ffixed-reg has special significance to the RX port when used with the "interrupt" function attribute. This attribute indicates a function intended to process fast interrupts. GCC ensures that it only uses the registers "r10", "r11", "r12" and/or "r13" and only provided that the normal use of the corresponding registers have been restricted via the -ffixed-reg or -mint-register command-line options.
S/390 and zSeries Options
These are the -m options defined for the S/390 and zSeries architecture.
-
-mhard-float
-
-
-msoft-float
-
Use (do not use) the hardware floating-point instructions and registers for floating-point operations. When -msoft-float is specified, functions in libgcc.a are used to perform floating-point operations. When -mhard-float is specified, the compiler generates IEEE floating-point instructions. This is the default.
-
-mhard-dfp
-
-
-mno-hard-dfp
-
Use (do not use) the hardware decimal-floating-point instructions for decimal-floating-point operations. When -mno-hard-dfp is specified, functions in libgcc.a are used to perform decimal-floating-point operations. When -mhard-dfp is specified, the compiler generates decimal-floating-point hardware instructions. This is the default for -march=z9-ec or higher.
-
-mlong-double-64
-
-
-mlong-double-128
-
These switches control the size of "long double" type. A size of 64 bits makes the "long double" type equivalent to the "double" type. This is the default.
-
-mbackchain
-
-
-mno-backchain
-
Store (do not store) the address of the caller's frame as backchain pointer into the callee's stack frame. A backchain may be needed to allow debugging using tools that do not understand DWARF 2 call frame information. When -mno-packed-stack is in effect, the backchain pointer is stored at the bottom of the stack frame; when -mpacked-stack is in effect, the backchain is placed into the topmost word of the 96/160 byte register save area.
In general, code compiled with -mbackchain is call-compatible with code compiled with -mmo-backchain; however, use of the backchain for debugging purposes usually requires that the whole binary is built with -mbackchain. Note that the combination of -mbackchain, -mpacked-stack and -mhard-float is not supported. In order to build a linux kernel use -msoft-float.
The default is to not maintain the backchain.
-
-mpacked-stack
-
-
-mno-packed-stack
-
Use (do not use) the packed stack layout. When -mno-packed-stack is specified, the compiler uses the all fields of the 96/160 byte register save area only for their default purpose; unused fields still take up stack space. When -mpacked-stack is specified, register save slots are densely packed at the top of the register save area; unused space is reused for other purposes, allowing for more efficient use of the available stack space. However, when -mbackchain is also in effect, the topmost word of the save area is always used to store the backchain, and the return address register is always saved two words below the backchain.
As long as the stack frame backchain is not used, code generated with -mpacked-stack is call-compatible with code generated with -mno-packed-stack. Note that some non-FSF releases of GCC 2.95 for S/390 or zSeries generated code that uses the stack frame backchain at run time, not just for debugging purposes. Such code is not call-compatible with code compiled with -mpacked-stack. Also, note that the combination of -mbackchain, -mpacked-stack and -mhard-float is not supported. In order to build a linux kernel use -msoft-float.
The default is to not use the packed stack layout.
-
-msmall-exec
-
-
-mno-small-exec
-
Generate (or do not generate) code using the "bras" instruction to do subroutine calls. This only works reliably if the total executable size does not exceed 64k. The default is to use the "basr" instruction instead, which does not have this limitation.
-
-m64
-
-
-m31
-
When -m31 is specified, generate code compliant to the GNU/Linux for S/390 ABI. When -m64 is specified, generate code compliant to the GNU/Linux for zSeries ABI. This allows GCC in particular to generate 64-bit instructions. For the s390 targets, the default is -m31, while the s390x targets default to -m64.
-
-mzarch
-
-
-mesa
-
When -mzarch is specified, generate code using the instructions available on z/Architecture. When -mesa is specified, generate code using the instructions available on ESA/390. Note that -mesa is not possible with -m64. When generating code compliant to the GNU/Linux for S/390 ABI, the default is -mesa. When generating code compliant to the GNU/Linux for zSeries ABI, the default is -mzarch.
-
-mmvcle
-
-
-mno-mvcle
-
Generate (or do not generate) code using the "mvcle" instruction to perform block moves. When -mno-mvcle is specified, use a "mvc" loop instead. This is the default unless optimizing for size.
-
-mdebug
-
-
-mno-debug
-
Print (or do not print) additional debug information when compiling. The default is to not print debug information.
-
-march=cpu-type
-
Generate code that runs on cpu-type, which is the name of a system representing a certain processor type. Possible values for cpu-type are g5, g6, z900, z990, z9-109, z9-ec and z10. When generating code using the instructions available on z/Architecture, the default is -march=z900. Otherwise, the default is -march=g5.
-
-mtune=cpu-type
-
Tune to cpu-type everything applicable about the generated code, except for the ABI and the set of available instructions. The list of cpu-type values is the same as for -march. The default is the value used for -march.
-
-mtpf-trace
-
-
-mno-tpf-trace
-
Generate code that adds (does not add) in TPF OS specific branches to trace routines in the operating system. This option is off by default, even when compiling for the TPF OS.
-
-mfused-madd
-
-
-mno-fused-madd
-
Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used.
-
-mwarn-framesize=framesize
-
Emit a warning if the current function exceeds the given frame size. Because this is a compile-time check it doesn't need to be a real problem when the program runs. It is intended to identify functions that most probably cause a stack overflow. It is useful to be used in an environment with limited stack size e.g. the linux kernel.
-
-mwarn-dynamicstack
-
Emit a warning if the function calls "alloca" or uses dynamically-sized arrays. This is generally a bad idea with a limited stack size.
-
-mstack-guard=stack-guard
-
-
-mstack-size=stack-size
-
If these options are provided the S/390 back end emits additional instructions in the function prologue that trigger a trap if the stack size is stack-guard bytes above the stack-size (remember that the stack on S/390 grows downward). If the stack-guard option is omitted the smallest power of 2 larger than the frame size of the compiled function is chosen. These options are intended to be used to help debugging stack overflow problems. The additionally emitted code causes only little overhead and hence can also be used in production-like systems without greater performance degradation. The given values have to be exact powers of 2 and stack-size has to be greater than stack-guard without exceeding 64k. In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by stack-size. The stack-guard option can only be used in conjunction with stack-size.
-
-mhotpatch[=halfwords]
-
-
-mno-hotpatch
-
If the hotpatch option is enabled, a "hot-patching" function prologue is generated for all functions in the compilation unit. The funtion label is prepended with the given number of two-byte Nop instructions ( halfwords, maximum 1000000) or 12 Nop instructions if no argument is present. Functions with a hot-patching prologue are never inlined automatically, and a hot-patching prologue is never generated for functions functions that are explicitly inline.
This option can be overridden for individual functions with the "hotpatch" attribute.
Score Options
These options are defined for Score implementations:
-
-meb
-
Compile code for big-endian mode. This is the default.
-
-mel
-
Compile code for little-endian mode.
-
-mnhwloop
-
Disable generation of "bcnz" instructions.
-
-muls
-
Enable generation of unaligned load and store instructions.
-
-mmac
-
Enable the use of multiply-accumulate instructions. Disabled by default.
-
-mscore5
-
Specify the SCORE5 as the target architecture.
-
-mscore5u
-
Specify the SCORE5U of the target architecture.
-
-mscore7
-
Specify the SCORE7 as the target architecture. This is the default.
-
-mscore7d
-
Specify the SCORE7D as the target architecture.
SH Options
These -m options are defined for the SH implementations:
-
-m1
-
Generate code for the SH1.
-
-m2
-
Generate code for the SH2.
-
-m2e
-
Generate code for the SH2e.
-
-m2a-nofpu
-
Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way that the floating-point unit is not used.
-
-m2a-single-only
-
Generate code for the SH2a-FPU, in such a way that no double-precision floating-point operations are used.
-
-m2a-single
-
Generate code for the SH2a-FPU assuming the floating-point unit is in single-precision mode by default.
-
-m2a
-
Generate code for the SH2a-FPU assuming the floating-point unit is in double-precision mode by default.
-
-m3
-
Generate code for the SH3.
-
-m3e
-
Generate code for the SH3e.
-
-m4-nofpu
-
Generate code for the SH4 without a floating-point unit.
-
-m4-single-only
-
Generate code for the SH4 with a floating-point unit that only supports single-precision arithmetic.
-
-m4-single
-
Generate code for the SH4 assuming the floating-point unit is in single-precision mode by default.
-
-m4
-
Generate code for the SH4.
-
-m4a-nofpu
-
Generate code for the SH4al-dsp, or for a SH4a in such a way that the floating-point unit is not used.
-
-m4a-single-only
-
Generate code for the SH4a, in such a way that no double-precision floating-point operations are used.
-
-m4a-single
-
Generate code for the SH4a assuming the floating-point unit is in single-precision mode by default.
-
-m4a
-
Generate code for the SH4a.
-
-m4al
-
Same as -m4a-nofpu, except that it implicitly passes -dsp to the assembler. GCC doesn't generate any DSP instructions at the moment.
-
-mb
-
Compile code for the processor in big-endian mode.
-
-ml
-
Compile code for the processor in little-endian mode.
-
-mdalign
-
Align doubles at 64-bit boundaries. Note that this changes the calling conventions, and thus some functions from the standard C library do not work unless you recompile it first with -mdalign.
-
-mrelax
-
Shorten some address references at link time, when possible; uses the linker option -relax.
-
-mbigtable
-
Use 32-bit offsets in "switch" tables. The default is to use 16-bit offsets.
-
-mbitops
-
Enable the use of bit manipulation instructions on SH2A.
-
-mfmovd
-
Enable the use of the instruction "fmovd". Check -mdalign for alignment constraints.
-
-mhitachi
-
Comply with the calling conventions defined by Renesas.
-
-mrenesas
-
Comply with the calling conventions defined by Renesas.
-
-mno-renesas
-
Comply with the calling conventions defined for GCC before the Renesas conventions were available. This option is the default for all targets of the SH toolchain.
-
-mnomacsave
-
Mark the "MAC" register as call-clobbered, even if -mhitachi is given.
-
-mieee
-
-
-mno-ieee
-
Control the IEEE compliance of floating-point comparisons, which affects the handling of cases where the result of a comparison is unordered. By default -mieee is implicitly enabled. If -ffinite-math-only is enabled -mno-ieee is implicitly set, which results in faster floating-point greater-equal and less-equal comparisons. The implcit settings can be overridden by specifying either -mieee or -mno-ieee.
-
-minline-ic_invalidate
-
Inline code to invalidate instruction cache entries after setting up nested function trampolines. This option has no effect if -musermode is in effect and the selected code generation option (e.g. -m4) does not allow the use of the "icbi" instruction. If the selected code generation option does not allow the use of the "icbi" instruction, and -musermode is not in effect, the inlined code manipulates the instruction cache address array directly with an associative write. This not only requires privileged mode at run time, but it also fails if the cache line had been mapped via the TLB and has become unmapped.
-
-misize
-
Dump instruction size and location in the assembly code.
-
-mpadstruct
-
This option is deprecated. It pads structures to multiple of 4 bytes, which is incompatible with the SH ABI.
-
-matomic-model=model
-
Sets the model of atomic operations and additional parameters as a comma separated list. For details on the atomic built-in functions see __atomic Builtins. The following models and parameters are supported:
-
none
-
Disable compiler generated atomic sequences and emit library calls for atomic operations. This is the default if the target is not "sh-*-linux*".
-
soft-gusa
-
Generate GNU/Linux compatible gUSA software atomic sequences for the atomic built-in functions. The generated atomic sequences require additional support from the interrupt/exception handling code of the system and are only suitable for SH3* and SH4* single-core systems. This option is enabled by default when the target is "sh-*-linux*" and SH3* or SH4*. When the target is SH4A, this option will also partially utilize the hardware atomic instructions "movli.l" and "movco.l" to create more efficient code, unless strict is specified.
-
soft-tcb
-
Generate software atomic sequences that use a variable in the thread control block. This is a variation of the gUSA sequences which can also be used on SH1* and SH2* targets. The generated atomic sequences require additional support from the interrupt/exception handling code of the system and are only suitable for single-core systems. When using this model, the gbr-offset= parameter has to be specified as well.
-
soft-imask
-
Generate software atomic sequences that temporarily disable interrupts by setting "SR.IMASK = 1111". This model works only when the program runs in privileged mode and is only suitable for single-core systems. Additional support from the interrupt/exception handling code of the system is not required. This model is enabled by default when the target is "sh-*-linux*" and SH1* or SH2*.
-
hard-llcs
-
Generate hardware atomic sequences using the "movli.l" and "movco.l" instructions only. This is only available on SH4A and is suitable for multi-core systems. Since the hardware instructions support only 32 bit atomic variables access to 8 or 16 bit variables is emulated with 32 bit accesses. Code compiled with this option will also be compatible with other software atomic model interrupt/exception handling systems if executed on an SH4A system. Additional support from the interrupt/exception handling code of the system is not required for this model.
-
gbr-offset=
-
This parameter specifies the offset in bytes of the variable in the thread control block structure that should be used by the generated atomic sequences when the soft-tcb model has been selected. For other models this parameter is ignored. The specified value must be an integer multiple of four and in the range 0-1020.
-
strict
-
This parameter prevents mixed usage of multiple atomic models, even though they would be compatible, and will make the compiler generate atomic sequences of the specified model only.
-
-mtas
-
Generate the "tas.b" opcode for "__atomic_test_and_set". Notice that depending on the particular hardware and software configuration this can degrade overall performance due to the operand cache line flushes that are implied by the "tas.b" instruction. On multi-core SH4A processors the "tas.b" instruction must be used with caution since it can result in data corruption for certain cache configurations.
-
-mspace
-
Optimize for space instead of speed. Implied by -Os.
-
-mprefergot
-
When generating position-independent code, emit function calls using the Global Offset Table instead of the Procedure Linkage Table.
-
-musermode
-
Don't generate privileged mode only code. This option implies -mno-inline-ic_invalidate if the inlined code would not work in user mode. This is the default when the target is "sh-*-linux*".
-
-multcost=number
-
Set the cost to assume for a multiply insn.
-
-mdiv=strategy
-
Set the division strategy to be used for integer division operations. For SHmedia strategy can be one of:
-
fp
-
Performs the operation in floating point. This has a very high latency, but needs only a few instructions, so it might be a good choice if your code has enough easily-exploitable ILP to allow the compiler to schedule the floating-point instructions together with other instructions. Division by zero causes a floating-point exception.
-
inv
-
Uses integer operations to calculate the inverse of the divisor, and then multiplies the dividend with the inverse. This strategy allows CSE and hoisting of the inverse calculation. Division by zero calculates an unspecified result, but does not trap.
-
inv:minlat
-
A variant of inv where, if no CSE or hoisting opportunities have been found, or if the entire operation has been hoisted to the same place, the last stages of the inverse calculation are intertwined with the final multiply to reduce the overall latency, at the expense of using a few more instructions, and thus offering fewer scheduling opportunities with other code.
-
call
-
Calls a library function that usually implements the inv:minlat strategy. This gives high code density for "m5-*media-nofpu" compilations.
-
call2
-
Uses a different entry point of the same library function, where it assumes that a pointer to a lookup table has already been set up, which exposes the pointer load to CSE and code hoisting optimizations.
-
inv:call
-
-
inv:call2
-
-
inv:fp
-
Use the inv algorithm for initial code generation, but if the code stays unoptimized, revert to the call, call2, or fp strategies, respectively. Note that the potentially-trapping side effect of division by zero is carried by a separate instruction, so it is possible that all the integer instructions are hoisted out, but the marker for the side effect stays where it is. A recombination to floating-point operations or a call is not possible in that case.
-
inv20u
-
-
inv20l
-
Variants of the inv:minlat strategy. In the case that the inverse calculation is not separated from the multiply, they speed up division where the dividend fits into 20 bits (plus sign where applicable) by inserting a test to skip a number of operations in this case; this test slows down the case of larger dividends. inv20u assumes the case of a such a small dividend to be unlikely, and inv20l assumes it to be likely.
For targets other than SHmedia
strategy can be one of:
-
call-div1
-
Calls a library function that uses the single-step division instruction "div1" to perform the operation. Division by zero calculates an unspecified result and does not trap. This is the default except for SH4, SH2A and SHcompact.
-
call-fp
-
Calls a library function that performs the operation in double precision floating point. Division by zero causes a floating-point exception. This is the default for SHcompact with FPU. Specifying this for targets that do not have a double precision FPU will default to "call-div1".
-
call-table
-
Calls a library function that uses a lookup table for small divisors and the "div1" instruction with case distinction for larger divisors. Division by zero calculates an unspecified result and does not trap. This is the default for SH4. Specifying this for targets that do not have dynamic shift instructions will default to "call-div1".
When a division strategy has not been specified the default strategy will be selected based on the current target. For SH2A the default strategy is to use the "divs" and "divu" instructions instead of library function calls.
-
-maccumulate-outgoing-args
-
Reserve space once for outgoing arguments in the function prologue rather than around each call. Generally beneficial for performance and size. Also needed for unwinding to avoid changing the stack frame around conditional code.
-
-mdivsi3_libfunc=name
-
Set the name of the library function used for 32-bit signed division to name. This only affects the name used in the call and inv:call division strategies, and the compiler still expects the same sets of input/output/clobbered registers as if this option were not present.
-
-mfixed-range=register-range
-
Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator can not use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.
-
-mindexed-addressing
-
Enable the use of the indexed addressing mode for SHmedia32/SHcompact. This is only safe if the hardware and/or OS implement 32-bit wrap-around semantics for the indexed addressing mode. The architecture allows the implementation of processors with 64-bit MMU, which the OS could use to get 32-bit addressing, but since no current hardware implementation supports this or any other way to make the indexed addressing mode safe to use in the 32-bit ABI, the default is -mno-indexed-addressing.
-
-mgettrcost=number
-
Set the cost assumed for the "gettr" instruction to number. The default is 2 if -mpt-fixed is in effect, 100 otherwise.
-
-mpt-fixed
-
Assume "pt*" instructions won't trap. This generally generates better-scheduled code, but is unsafe on current hardware. The current architecture definition says that "ptabs" and "ptrel" trap when the target anded with 3 is 3. This has the unintentional effect of making it unsafe to schedule these instructions before a branch, or hoist them out of a loop. For example, "__do_global_ctors", a part of libgcc that runs constructors at program startup, calls functions in a list which is delimited by -1. With the -mpt-fixed option, the "ptabs" is done before testing against -1. That means that all the constructors run a bit more quickly, but when the loop comes to the end of the list, the program crashes because "ptabs" loads -1 into a target register.
Since this option is unsafe for any hardware implementing the current architecture specification, the default is -mno-pt-fixed. Unless specified explicitly with -mgettrcost, -mno-pt-fixed also implies -mgettrcost=100; this deters register allocation from using target registers for storing ordinary integers.
-
-minvalid-symbols
-
Assume symbols might be invalid. Ordinary function symbols generated by the compiler are always valid to load with "movi"/"shori"/"ptabs" or "movi"/"shori"/"ptrel", but with assembler and/or linker tricks it is possible to generate symbols that cause "ptabs" or "ptrel" to trap. This option is only meaningful when -mno-pt-fixed is in effect. It prevents cross-basic-block CSE, hoisting and most scheduling of symbol loads. The default is -mno-invalid-symbols.
-
-mbranch-cost=num
-
Assume num to be the cost for a branch instruction. Higher numbers make the compiler try to generate more branch-free code if possible. If not specified the value is selected depending on the processor type that is being compiled for.
-
-mzdcbranch
-
-
-mno-zdcbranch
-
Assume (do not assume) that zero displacement conditional branch instructions "bt" and "bf" are fast. If -mzdcbranch is specified, the compiler will try to prefer zero displacement branch code sequences. This is enabled by default when generating code for SH4 and SH4A. It can be explicitly disabled by specifying -mno-zdcbranch.
-
-mcbranchdi
-
Enable the "cbranchdi4" instruction pattern.
-
-mcmpeqdi
-
Emit the "cmpeqdi_t" instruction pattern even when -mcbranchdi is in effect.
-
-mfused-madd
-
-
-mno-fused-madd
-
Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used. The machine-dependent -mfused-madd option is now mapped to the machine-independent -ffp-contract=fast option, and -mno-fused-madd is mapped to -ffp-contract=off.
-
-mfsca
-
-
-mno-fsca
-
Allow or disallow the compiler to emit the "fsca" instruction for sine and cosine approximations. The option "-mfsca" must be used in combination with "-funsafe-math-optimizations". It is enabled by default when generating code for SH4A. Using "-mno-fsca" disables sine and cosine approximations even if "-funsafe-math-optimizations" is in effect.
-
-mfsrra
-
-
-mno-fsrra
-
Allow or disallow the compiler to emit the "fsrra" instruction for reciprocal square root approximations. The option "-mfsrra" must be used in combination with "-funsafe-math-optimizations" and "-ffinite-math-only". It is enabled by default when generating code for SH4A. Using "-mno-fsrra" disables reciprocal square root approximations even if "-funsafe-math-optimizations" and "-ffinite-math-only" are in effect.
-
-mpretend-cmove
-
Prefer zero-displacement conditional branches for conditional move instruction patterns. This can result in faster code on the SH4 processor.
Solaris 2 Options
These -m options are supported on Solaris 2:
-
-mimpure-text
-
-mimpure-text, used in addition to -shared, tells the compiler to not pass -z text to the linker when linking a shared object. Using this option, you can link position-dependent code into a shared object.
-mimpure-text suppresses the "relocations remain against allocatable but non-writable sections" linker error message. However, the necessary relocations trigger copy-on-write, and the shared object is not actually shared across processes. Instead of using -mimpure-text, you should compile all source code with -fpic or -fPIC.
These switches are supported in addition to the above on Solaris 2:
-
-pthreads
-
Add support for multithreading using the POSIX threads library. This option sets flags for both the preprocessor and linker. This option does not affect the thread safety of object code produced by the compiler or that of libraries supplied with it.
-
-pthread
-
This is a synonym for -pthreads.
SPARC Options
These -m options are supported on the SPARC:
-
-mno-app-regs
-
-
-mapp-regs
-
Specify -mapp-regs to generate output using the global registers 2 through 4, which the SPARC SVR4 ABI reserves for applications. This is the default.
To be fully SVR4 ABI-compliant at the cost of some performance loss, specify -mno-app-regs. You should compile libraries and system software with this option.
-
-mflat
-
-
-mno-flat
-
With -mflat, the compiler does not generate save/restore instructions and uses a "flat" or single register window model. This model is compatible with the regular register window model. The local registers and the input registers (0--5) are still treated as "call-saved" registers and are saved on the stack as needed.
With -mno-flat (the default), the compiler generates save/restore instructions (except for leaf functions). This is the normal operating mode.
-
-mfpu
-
-
-mhard-float
-
Generate output containing floating-point instructions. This is the default.
-
-mno-fpu
-
-
-msoft-float
-
Generate output containing library calls for floating point. Warning: the requisite libraries are not available for all SPARC targets. Normally the facilities of the machine's usual C compiler are used, but this cannot be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation. The embedded targets sparc-*-aout and sparclite-*-* do provide software floating-point support.
-msoft-float changes the calling convention in the output file; therefore, it is only useful if you compile all of a program with this option. In particular, you need to compile libgcc.a, the library that comes with GCC, with -msoft-float in order for this to work.
-
-mhard-quad-float
-
Generate output containing quad-word (long double) floating-point instructions.
-
-msoft-quad-float
-
Generate output containing library calls for quad-word (long double) floating-point instructions. The functions called are those specified in the SPARC ABI. This is the default.
As of this writing, there are no SPARC implementations that have hardware support for the quad-word floating-point instructions. They all invoke a trap handler for one of these instructions, and then the trap handler emulates the effect of the instruction. Because of the trap handler overhead, this is much slower than calling the ABI library routines. Thus the -msoft-quad-float option is the default.
-
-mno-unaligned-doubles
-
-
-munaligned-doubles
-
Assume that doubles have 8-byte alignment. This is the default.
With -munaligned-doubles, GCC assumes that doubles have 8-byte alignment only if they are contained in another type, or if they have an absolute address. Otherwise, it assumes they have 4-byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code.
-
-mno-faster-structs
-
-
-mfaster-structs
-
With -mfaster-structs, the compiler assumes that structures should have 8-byte alignment. This enables the use of pairs of "ldd" and "std" instructions for copies in structure assignment, in place of twice as many "ld" and "st" pairs. However, the use of this changed alignment directly violates the SPARC ABI. Thus, it's intended only for use on targets where the developer acknowledges that their resulting code is not directly in line with the rules of the ABI.
-
-mcpu=cpu_type
-
Set the instruction set, register set, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are v7, cypress, v8, supersparc, hypersparc, leon, leon3, sparclite, f930, f934, sparclite86x, sparclet, tsc701, v9, ultrasparc, ultrasparc3, niagara, niagara2, niagara3 and niagara4.
Native Solaris and GNU/Linux toolchains also support the value native, which selects the best architecture option for the host processor. -mcpu=native has no effect if GCC does not recognize the processor.
Default instruction scheduling parameters are used for values that select an architecture and not an implementation. These are v7, v8, sparclite, sparclet, v9.
Here is a list of each supported architecture and their supported implementations.
-
v7
-
cypress
-
v8
-
supersparc, hypersparc, leon, leon3
-
sparclite
-
f930, f934, sparclite86x
-
sparclet
-
tsc701
-
v9
-
ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
By default (unless configured otherwise), GCC generates code for the V7 variant of the SPARC architecture. With
-mcpu=cypress, the compiler additionally optimizes it for the Cypress CY7C602 chip, as used in the SPARCStation/SPARCServer 3xx series. This is also appropriate for the older SPARCStation 1, 2, IPX etc.
With
-mcpu=v8, GCC generates code for the V8 variant of the SPARC architecture. The only difference from V7 code is that the compiler emits the integer multiply and integer divide instructions which exist in SPARC-V8 but not in SPARC-V7. With
-mcpu=supersparc, the compiler additionally optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and 2000 series.
With
-mcpu=sparclite, GCC generates code for the SPARClite variant of the SPARC architecture. This adds the integer multiply, integer divide step and scan ("ffs") instructions which exist in SPARClite but not in SPARC-V7. With
-mcpu=f930, the compiler additionally optimizes it for the Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With
-mcpu=f934, the compiler additionally optimizes it for the Fujitsu MB86934 chip, which is the more recent SPARClite with FPU.
With
-mcpu=sparclet, GCC generates code for the SPARClet variant of the SPARC architecture. This adds the integer multiply, multiply/accumulate, integer divide step and scan ("ffs") instructions which exist in SPARClet but not in SPARC-V7. With
-mcpu=tsc701, the compiler additionally optimizes it for the TEMIC SPARClet chip.
With
-mcpu=v9, GCC generates code for the V9 variant of the SPARC architecture. This adds 64-bit integer and floating-point move instructions, 3 additional floating-point condition code registers and conditional move instructions. With
-mcpu=ultrasparc, the compiler additionally optimizes it for the Sun UltraSPARC I/II/IIi chips. With
-mcpu=ultrasparc3, the compiler additionally optimizes it for the Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
-mcpu=niagara, the compiler additionally optimizes it for Sun UltraSPARC T1 chips. With
-mcpu=niagara2, the compiler additionally optimizes it for Sun UltraSPARC T2 chips. With
-mcpu=niagara3, the compiler additionally optimizes it for Sun UltraSPARC T3 chips. With
-mcpu=niagara4, the compiler additionally optimizes it for Sun UltraSPARC T4 chips.
-
-mtune=cpu_type
-
Set the instruction scheduling parameters for machine type cpu_type, but do not set the instruction set or register set that the option -mcpu=cpu_type does.
The same values for -mcpu=cpu_type can be used for -mtune=cpu_type, but the only useful values are those that select a particular CPU implementation. Those are cypress, supersparc, hypersparc, leon, leon3, f930, f934, sparclite86x, tsc701, ultrasparc, ultrasparc3, niagara, niagara2, niagara3 and niagara4. With native Solaris and GNU/Linux toolchains, native can also be used.
-
-mv8plus
-
-
-mno-v8plus
-
With -mv8plus, GCC generates code for the SPARC-V8+ ABI. The difference from the V8 ABI is that the global and out registers are considered 64 bits wide. This is enabled by default on Solaris in 32-bit mode for all SPARC-V9 processors.
-
-mvis
-
-
-mno-vis
-
With -mvis, GCC generates code that takes advantage of the UltraSPARC Visual Instruction Set extensions. The default is -mno-vis.
-
-mvis2
-
-
-mno-vis2
-
With -mvis2, GCC generates code that takes advantage of version 2.0 of the UltraSPARC Visual Instruction Set extensions. The default is -mvis2 when targeting a cpu that supports such instructions, such as UltraSPARC-III and later. Setting -mvis2 also sets -mvis.
-
-mvis3
-
-
-mno-vis3
-
With -mvis3, GCC generates code that takes advantage of version 3.0 of the UltraSPARC Visual Instruction Set extensions. The default is -mvis3 when targeting a cpu that supports such instructions, such as niagara-3 and later. Setting -mvis3 also sets -mvis2 and -mvis.
-
-mcbcond
-
-
-mno-cbcond
-
With -mcbcond, GCC generates code that takes advantage of compare-and-branch instructions, as defined in the Sparc Architecture 2011. The default is -mcbcond when targeting a cpu that supports such instructions, such as niagara-4 and later.
-
-mpopc
-
-
-mno-popc
-
With -mpopc, GCC generates code that takes advantage of the UltraSPARC population count instruction. The default is -mpopc when targeting a cpu that supports such instructions, such as Niagara-2 and later.
-
-mfmaf
-
-
-mno-fmaf
-
With -mfmaf, GCC generates code that takes advantage of the UltraSPARC Fused Multiply-Add Floating-point extensions. The default is -mfmaf when targeting a cpu that supports such instructions, such as Niagara-3 and later.
-
-mfix-at697f
-
Enable the documented workaround for the single erratum of the Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor).
-
-mfix-ut699
-
Enable the documented workarounds for the floating-point errata and the data cache nullify errata of the UT699 processor.
These -m options are supported in addition to the above on SPARC-V9 processors in 64-bit environments:
-
-m32
-
-
-m64
-
Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits.
-
-mcmodel=which
-
Set the code model to one of
-
medlow
-
The Medium/Low code model: 64-bit addresses, programs must be linked in the low 32 bits of memory. Programs can be statically or dynamically linked.
-
medmid
-
The Medium/Middle code model: 64-bit addresses, programs must be linked in the low 44 bits of memory, the text and data segments must be less than 2GB in size and the data segment must be located within 2GB of the text segment.
-
medany
-
The Medium/Anywhere code model: 64-bit addresses, programs may be linked anywhere in memory, the text and data segments must be less than 2GB in size and the data segment must be located within 2GB of the text segment.
-
embmedany
-
The Medium/Anywhere code model for embedded systems: 64-bit addresses, the text and data segments must be less than 2GB in size, both starting anywhere in memory (determined at link time). The global register %g4 points to the base of the data segment. Programs are statically linked and PIC is not supported.
-
-mmemory-model=mem-model
-
Set the memory model in force on the processor to one of
-
default
-
The default memory model for the processor and operating system.
-
rmo
-
Relaxed Memory Order
-
pso
-
Partial Store Order
-
tso
-
Total Store Order
-
sc
-
Sequential Consistency
These memory models are formally defined in Appendix D of the Sparc V9 architecture manual, as set in the processor's "PSTATE.MM" field.
-
-mstack-bias
-
-
-mno-stack-bias
-
With -mstack-bias, GCC assumes that the stack pointer, and frame pointer if present, are offset by -2047 which must be added back when making stack frame references. This is the default in 64-bit mode. Otherwise, assume no such offset is present.
SPU Options
These -m options are supported on the SPU:
-
-mwarn-reloc
-
-
-merror-reloc
-
The loader for SPU does not handle dynamic relocations. By default, GCC gives an error when it generates code that requires a dynamic relocation. -mno-error-reloc disables the error, -mwarn-reloc generates a warning instead.
-
-msafe-dma
-
-
-munsafe-dma
-
Instructions that initiate or test completion of DMA must not be reordered with respect to loads and stores of the memory that is being accessed. With -munsafe-dma you must use the "volatile" keyword to protect memory accesses, but that can lead to inefficient code in places where the memory is known to not change. Rather than mark the memory as volatile, you can use -msafe-dma to tell the compiler to treat the DMA instructions as potentially affecting all memory.
-
-mbranch-hints
-
By default, GCC generates a branch hint instruction to avoid pipeline stalls for always-taken or probably-taken branches. A hint is not generated closer than 8 instructions away from its branch. There is little reason to disable them, except for debugging purposes, or to make an object a little bit smaller.
-
-msmall-mem
-
-
-mlarge-mem
-
By default, GCC generates code assuming that addresses are never larger than 18 bits. With -mlarge-mem code is generated that assumes a full 32-bit address.
-
-mstdmain
-
By default, GCC links against startup code that assumes the SPU-style main function interface (which has an unconventional parameter list). With -mstdmain, GCC links your program against startup code that assumes a C99-style interface to "main", including a local copy of "argv" strings.
-
-mfixed-range=register-range
-
Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.
-
-mea32
-
-
-mea64
-
Compile code assuming that pointers to the PPU address space accessed via the "__ea" named address space qualifier are either 32 or 64 bits wide. The default is 32 bits. As this is an ABI-changing option, all object code in an executable must be compiled with the same setting.
-
-maddress-space-conversion
-
-
-mno-address-space-conversion
-
Allow/disallow treating the "__ea" address space as superset of the generic address space. This enables explicit type casts between "__ea" and generic pointer as well as implicit conversions of generic pointers to "__ea" pointers. The default is to allow address space pointer conversions.
-
-mcache-size=cache-size
-
This option controls the version of libgcc that the compiler links to an executable and selects a software-managed cache for accessing variables in the "__ea" address space with a particular cache size. Possible options for cache-size are 8, 16, 32, 64 and 128. The default cache size is 64KB.
-
-matomic-updates
-
-
-mno-atomic-updates
-
This option controls the version of libgcc that the compiler links to an executable and selects whether atomic updates to the software-managed cache of PPU-side variables are used. If you use atomic updates, changes to a PPU variable from SPU code using the "__ea" named address space qualifier do not interfere with changes to other PPU variables residing in the same cache line from PPU code. If you do not use atomic updates, such interference may occur; however, writing back cache lines is more efficient. The default behavior is to use atomic updates.
-
-mdual-nops
-
-
-mdual-nops=n
-
By default, GCC inserts nops to increase dual issue when it expects it to increase performance. n can be a value from 0 to 10. A smaller n inserts fewer nops. 10 is the default, 0 is the same as -mno-dual-nops. Disabled with -Os.
-
-mhint-max-nops=n
-
Maximum number of nops to insert for a branch hint. A branch hint must be at least 8 instructions away from the branch it is affecting. GCC inserts up to n nops to enforce this, otherwise it does not generate the branch hint.
-
-mhint-max-distance=n
-
The encoding of the branch hint instruction limits the hint to be within 256 instructions of the branch it is affecting. By default, GCC makes sure it is within 125.
-
-msafe-hints
-
Work around a hardware bug that causes the SPU to stall indefinitely. By default, GCC inserts the "hbrp" instruction to make sure this stall won't happen.
Options for System V
These additional options are available on System V Release 4 for compatibility with other compilers on those systems:
-
-G
-
Create a shared object. It is recommended that -symbolic or -shared be used instead.
-
-Qy
-
Identify the versions of each tool used by the compiler, in a ".ident" assembler directive in the output.
-
-Qn
-
Refrain from adding ".ident" directives to the output file (this is the default).
-
-YP,dirs
-
Search the directories dirs, and no others, for libraries specified with -l.
-
-Ym,dir
-
Look in the directory dir to find the M4 preprocessor. The assembler uses this option.
TILE-Gx Options
These -m options are supported on the TILE-Gx:
-
-mcmodel=small
-
Generate code for the small model. The distance for direct calls is limited to 500M in either direction. PC-relative addresses are 32 bits. Absolute addresses support the full address range.
-
-mcmodel=large
-
Generate code for the large model. There is no limitation on call distance, pc-relative addresses, or absolute addresses.
-
-mcpu=name
-
Selects the type of CPU to be targeted. Currently the only supported type is tilegx.
-
-m32
-
-
-m64
-
Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long, and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits.
TILEPro Options
These -m options are supported on the TILEPro:
-
-mcpu=name
-
Selects the type of CPU to be targeted. Currently the only supported type is tilepro.
-
-m32
-
Generate code for a 32-bit environment, which sets int, long, and pointer to 32 bits. This is the only supported behavior so the flag is essentially ignored.
V850 Options
These -m options are defined for V850 implementations:
-
-mlong-calls
-
-
-mno-long-calls
-
Treat all calls as being far away (near). If calls are assumed to be far away, the compiler always loads the function's address into a register, and calls indirect through the pointer.
-
-mno-ep
-
-
-mep
-
Do not optimize (do optimize) basic blocks that use the same index pointer 4 or more times to copy pointer into the "ep" register, and use the shorter "sld" and "sst" instructions. The -mep option is on by default if you optimize.
-
-mno-prolog-function
-
-
-mprolog-function
-
Do not use (do use) external functions to save and restore registers at the prologue and epilogue of a function. The external functions are slower, but use less code space if more than one function saves the same number of registers. The -mprolog-function option is on by default if you optimize.
-
-mspace
-
Try to make the code as small as possible. At present, this just turns on the -mep and -mprolog-function options.
-
-mtda=n
-
Put static or global variables whose size is n bytes or less into the tiny data area that register "ep" points to. The tiny data area can hold up to 256 bytes in total (128 bytes for byte references).
-
-msda=n
-
Put static or global variables whose size is n bytes or less into the small data area that register "gp" points to. The small data area can hold up to 64 kilobytes.
-
-mzda=n
-
Put static or global variables whose size is n bytes or less into the first 32 kilobytes of memory.
-
-mv850
-
Specify that the target processor is the V850.
-
-mv850e3v5
-
Specify that the target processor is the V850E3V5. The preprocessor constant __v850e3v5__ is defined if this option is used.
-
-mv850e2v4
-
Specify that the target processor is the V850E3V5. This is an alias for the -mv850e3v5 option.
-
-mv850e2v3
-
Specify that the target processor is the V850E2V3. The preprocessor constant __v850e2v3__ is defined if this option is used.
-
-mv850e2
-
Specify that the target processor is the V850E2. The preprocessor constant __v850e2__ is defined if this option is used.
-
-mv850e1
-
Specify that the target processor is the V850E1. The preprocessor constants __v850e1__ and __v850e__ are defined if this option is used.
-
-mv850es
-
Specify that the target processor is the V850ES. This is an alias for the -mv850e1 option.
-
-mv850e
-
Specify that the target processor is the V850E. The preprocessor constant __v850e__ is defined if this option is used.
If neither -mv850 nor -mv850e nor -mv850e1 nor -mv850e2 nor -mv850e2v3 nor -mv850e3v5 are defined then a default target processor is chosen and the relevant __v850*__ preprocessor constant is defined.
The preprocessor constants __v850 and __v851__ are always defined, regardless of which processor variant is the target.
-
-mdisable-callt
-
-
-mno-disable-callt
-
This option suppresses generation of the "CALLT" instruction for the v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 architecture.
This option is enabled by default when the RH850 ABI is in use (see -mrh850-abi), and disabled by default when the GCC ABI is in use. If "CALLT" instructions are being generated then the C preprocessor symbol "__V850_CALLT__" will be defined.
-
-mrelax
-
-
-mno-relax
-
Pass on (or do not pass on) the -mrelax command line option to the assembler.
-
-mlong-jumps
-
-
-mno-long-jumps
-
Disable (or re-enable) the generation of PC-relative jump instructions.
-
-msoft-float
-
-
-mhard-float
-
Disable (or re-enable) the generation of hardware floating point instructions. This option is only significant when the target architecture is V850E2V3 or higher. If hardware floating point instructions are being generated then the C preprocessor symbol "__FPU_OK__" will be defined, otherwise the symbol "__NO_FPU__" will be defined.
-
-mloop
-
Enables the use of the e3v5 LOOP instruction. The use of this instruction is not enabled by default when the e3v5 architecture is selected because its use is still experimental.
-
-mrh850-abi
-
-
-mghs
-
Enables support for the RH850 version of the V850 ABI. This is the default. With this version of the ABI the following rules apply:
-
•
-
Integer sized structures and unions are returned via a memory pointer rather than a register.
-
•
-
Large structures and unions (more than 8 bytes in size) are passed by value.
-
•
-
Functions are aligned to 16-bit boundaries.
-
•
-
The -m8byte-align command line option is supported.
-
•
-
The -mdisable-callt command line option is enabled by default. The -mno-disable-callt command line option is not supported.
When this version of the ABI is enabled the C preprocessor symbol "__V850_RH850_ABI__" is defined.
-
-mgcc-abi
-
Enables support for the old GCC version of the V850 ABI. With this version of the ABI the following rules apply:
-
•
-
Integer sized structures and unions are returned in register "r10".
-
•
-
Large structures and unions (more than 8 bytes in size) are passed by reference.
-
•
-
Functions are aligned to 32-bit boundaries, unless optimizing for size.
-
•
-
The -m8byte-align command line option is not supported.
-
•
-
The -mdisable-callt command line option is supported but not enabled by default.
When this version of the ABI is enabled the C preprocessor symbol "__V850_GCC_ABI__" is defined.
-
-m8byte-align
-
-
-mno-8byte-align
-
Enables support for "doubles" and "long long" types to be aligned on 8-byte boundaries. The default is to restrict the alignment of all objects to at most 4-bytes. When -m8byte-align is in effect the C preprocessor symbol "__V850_8BYTE_ALIGN__" will be defined.
-
-mbig-switch
-
Generate code suitable for big switch tables. Use this option only if the assembler/linker complain about out of range branches within a switch table.
-
-mapp-regs
-
This option causes r2 and r5 to be used in the code generated by the compiler. This setting is the default.
-
-mno-app-regs
-
This option causes r2 and r5 to be treated as fixed registers.
VAX Options
These -m options are defined for the VAX:
-
-munix
-
Do not output certain jump instructions ("aobleq" and so on) that the Unix assembler for the VAX cannot handle across long ranges.
-
-mgnu
-
Do output those jump instructions, on the assumption that the GNU assembler is being used.
-
-mg
-
Output code for G-format floating-point numbers instead of D-format.
VMS Options
These -m options are defined for the VMS implementations:
-
-mvms-return-codes
-
Return VMS condition codes from "main". The default is to return POSIX-style condition (e.g. error) codes.
-
-mdebug-main=prefix
-
Flag the first routine whose name starts with prefix as the main routine for the debugger.
-
-mmalloc64
-
Default to 64-bit memory allocation routines.
-
-mpointer-size=size
-
Set the default size of pointers. Possible options for size are 32 or short for 32 bit pointers, 64 or long for 64 bit pointers, and no for supporting only 32 bit pointers. The later option disables "pragma pointer_size".
VxWorks Options
The options in this section are defined for all VxWorks targets. Options specific to the target hardware are listed with the other options for that target.
-
-mrtp
-
GCC can generate code for both VxWorks kernels and real time processes (RTPs). This option switches from the former to the latter. It also defines the preprocessor macro "__RTP__".
-
-non-static
-
Link an RTP executable against shared libraries rather than static libraries. The options -static and -shared can also be used for RTPs; -static is the default.
-
-Bstatic
-
-
-Bdynamic
-
These options are passed down to the linker. They are defined for compatibility with Diab.
-
-Xbind-lazy
-
Enable lazy binding of function calls. This option is equivalent to -Wl,-z,now and is defined for compatibility with Diab.
-
-Xbind-now
-
Disable lazy binding of function calls. This option is the default and is defined for compatibility with Diab.
x86-64 Options
These are listed under
Xstormy16 Options
These options are defined for Xstormy16:
-
-msim
-
Choose startup files and linker script suitable for the simulator.
Xtensa Options
These options are supported for Xtensa targets:
-
-mconst16
-
-
-mno-const16
-
Enable or disable use of "CONST16" instructions for loading constant values. The "CONST16" instruction is currently not a standard option from Tensilica. When enabled, "CONST16" instructions are always used in place of the standard "L32R" instructions. The use of "CONST16" is enabled by default only if the "L32R" instruction is not available.
-
-mfused-madd
-
-
-mno-fused-madd
-
Enable or disable use of fused multiply/add and multiply/subtract instructions in the floating-point option. This has no effect if the floating-point option is not also enabled. Disabling fused multiply/add and multiply/subtract instructions forces the compiler to use separate instructions for the multiply and add/subtract operations. This may be desirable in some cases where strict IEEE 754-compliant results are required: the fused multiply add/subtract instructions do not round the intermediate result, thereby producing results with more bits of precision than specified by the IEEE standard. Disabling fused multiply add/subtract instructions also ensures that the program output is not sensitive to the compiler's ability to combine multiply and add/subtract operations.
-
-mserialize-volatile
-
-
-mno-serialize-volatile
-
When this option is enabled, GCC inserts "MEMW" instructions before "volatile" memory references to guarantee sequential consistency. The default is -mserialize-volatile. Use -mno-serialize-volatile to omit the "MEMW" instructions.
-
-mforce-no-pic
-
For targets, like GNU/Linux, where all user-mode Xtensa code must be position-independent code (PIC), this option disables PIC for compiling kernel code.
-
-mtext-section-literals
-
-
-mno-text-section-literals
-
Control the treatment of literal pools. The default is -mno-text-section-literals, which places literals in a separate section in the output file. This allows the literal pool to be placed in a data RAM/ROM, and it also allows the linker to combine literal pools from separate object files to remove redundant literals and improve code size. With -mtext-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files.
-
-mtarget-align
-
-
-mno-target-align
-
When this option is enabled, GCC instructs the assembler to automatically align instructions to reduce branch penalties at the expense of some code density. The assembler attempts to widen density instructions to align branch targets and the instructions following call instructions. If there are not enough preceding safe density instructions to align a target, no widening is performed. The default is -mtarget-align. These options do not affect the treatment of auto-aligned instructions like "LOOP", which the assembler always aligns, either by widening density instructions or by inserting NOP instructions.
-
-mlongcalls
-
-
-mno-longcalls
-
When this option is enabled, GCC instructs the assembler to translate direct calls to indirect calls unless it can determine that the target of a direct call is in the range allowed by the call instruction. This translation typically occurs for calls to functions in other source files. Specifically, the assembler translates a direct "CALL" instruction into an "L32R" followed by a "CALLX" instruction. The default is -mno-longcalls. This option should be used in programs where the call target can potentially be out of range. This option is implemented in the assembler, not the compiler, so the assembly code generated by GCC still shows direct call instructions---look at the disassembled object code to see the actual instructions. Note that the assembler uses an indirect call for every cross-file call, not just those that really are out of range.
zSeries Options
These are listed under